CS4210 datasheet(85/102 Pages) NSC

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4.4.26.2 Isoch Transmit Command Pointer

The CommandPtr register (Table 4-51) specifies the

address of the context program which is executed when a

ITDMA context is started. All descriptors are 16-byte

aligned, so the four least-significant bits of any descriptor

address must be zero. The four least-significant bits of the

CommandPtr register are used to encode a Z value that

indicates how many physically contiguous descriptors are

pointed to by descriptorAddress.

These registers are repeated at offsets of 10h times the

context number (see Table 4-49 on page 84 for offset

address assignment).

Table 4-50. IsochTxnContextControl Set/Clear Register

Bit

Name

Access

Reset

Description

cycleMatchEnable

RSCU

Undef

Cycle Match Enable: When set to one, processing occurs such that the

packet described by the context’s first descriptor block is transmitted in the

cycle whose number is specified in the cycleMatch field of this register. The

15-bit cycleMatch field must match the low order two bits of cycleSeconds

and the 13-bit cycleCount field in the cycle start packet that is sent or

received immediately before isochronous transmission begins. Since the

ITDMA controller may work ahead, the processing of the first descriptor

block may begin slightly in advance of the actual cycle in which the first

packet is transmitted. The effects of this bit are impacted by the values of

other bits in this register and are explained in descriptions below. Once the

context has become active, hardware clears the cycleMatchEnable bit.

30:16

cycleMatch

RSC

Undef

Cycle Match: Contains a 15-bit value, corresponding to the low order two

bits of the bus IsochCycleTimer.cycleSeconds and the 13-bit IsochCy-

cleTimer.cycleCount field (BAR0+Offset F0h). If ContextControl.cycleM-

atchEnable is set, then this ITDMA context becomes enabled for transmits

when the low order two bits of the bus IsochCycleTimer.cycleSeconds and

IsochCycleTimer.cycleCount value equals the cycleMatch value.

run

RSCU

Run: The run bit is set by software to enable descriptor processing for a

context and cleared by software to stop descriptor processing. The CS4210

only changes this bit on a hardware or software reset to set it to 0. See Sec-

tion 3.3.2.1 "ContextControl.run" on page 21 for details.

14:13

RSVD

Reserved

wake

RSU

Undef

Wake: Software sets this bit to 1 to cause the CS4210 to continue or

resume descriptor processing. The CS4210 clears this bit on every descrip-

tor fetch. See Section 3.3.2.2 "ContextControl.wake" on page 21 for details.

dead

Dead: The CS4210 sets this bit when it encounters a fatal error and clears

this bit when software clears the run bit. See Section 3.3.2.4 "ContextCon-

trol.dead" on page 21 for details.

active

Active: The CS4210 sets this bit to 1 when it is processing descriptors. See

Section 3.3.2.3 "ContextControl.active" on page 21 for details.

9:5

RSVD

Reserved

4:0

event code

Undef

Event Code: Following an OUTPUT_LAST* command, the error code is

indicated in this field. Possible values are: ack_complete, evt_underrun,

evt_descriptor_read, evt_data_read, evt_tcode_err and evt_unknown.

Table 4-51. IsochTxnCommandPtr Register

Bit

Name

Access

Reset

Description

31:4

descriptorAddress

RWU

Undef

Descriptor Address: Contains the upper 28 bits of the address of a 16-

byte aligned descriptor block. See Section 3.3.2.5 "CommandPtr" on page

22 for details.

3:0

RWU

Undef

Z: Indicates the number of contiguous 16-byte aligned blocks at the

address pointed to by descriptorAddress. If Z is 0, it indicates that the

descriptorAddress is not valid.

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