CS4210 datasheet(61/102 Pages) NSC

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4.4.5

Configuration ROM Header Register

The configuration ROM header register (Table 4-14) is a

32-bit number that externally maps to the 1st quadlet of the

1394

configuration

ROM

(1394

address

offset

FFFF_F000_0400h). This register is written locally at

BAR0+Offset 18h.

4.4.6

Bus Identification Register

The Bus Identification register (Table 4-15) is a 32-bit num-

ber that externally maps to the first quadlet of the

Bus_Info_Block.

Table 4-14. BAR0+Offset 18h: ConfigROMhdr Register

Bit

Name

Access

Reset

Description

31:24

info_length

RWU

00h

Information Length: IEEE 1394 bus management field. Must be valid at

any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.

23:!6

crc_length

RWU

00h

Cyclical Redundancy Check Length: IEEE 1394 bus management field.

Must be valid at any time the HCControl.linkEnable bit (BAR0+Offset

50h[17]) is set.

15:0

rom_crc_value

RWU

0000h

ROM Cyclical Redundancy Check Value: IEEE 1394 bus management

field. Must be valid at any time the HCControl.linkEnable bit (BAR0+Offset

50h[17]) is set.

Table 4-15. BAR0+Offset 1Ch: Bus Identification Register

Bit

Name

Access

Reset

Description

31:0

busID

31333934h

Bus Identification: This 32-bit number externally maps to the first quadlet of

the Bus_Info_Block. It contains the constant 31333934h which is the ASCII

value for “1394”.

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