CS4210 datasheet(46/102 Pages) NSC

46 / 102 page

www.national.com

Revision 1.0

Index 46h-47h

Power Management Capabilities Register

This register specifies capabilities related to PCI power management. This register is available only if the PCICapabilities bit (BAR1 Off-

set 00h[20]) is set in the nscControl register.

15:11

pmeSupport

01000

Power Management Event Support: Bit 14 is one indicating PME# may

be asserted from the D3HOT power state. PME# is not capable of asserting

from other states.

d2Support

D2 Power State Support: This bit reads zero indicating that the D2 power

state is not supported.

d1Support

D1 Power State Support: This bit reads zero indicating that the D1 power

state is not supported.

dynData

Dynamic Power Consumption Data: This bit reads zero indicating that

dynamic power consumption data is not provided.

7:6

RSVD

Reserved

5DSI

Driver Special Initialization: This bit reads zero indicating that no special

initialization is required beyond the standard PCI configuration header

before a generic class driver is able to use the CS4210.

auxPower

Auxiliary Power: This bit reads zero indicating that PME# generation in the

D3COLD state is not supported.

3pmeCLK

Power Management Event Clock: This bit reads zero indicating that no

host bus clock is required to generate PME#.

2:0

pmVerson

000

Power Management Version: This field reads zero indicating compatibility

with the PCI Bus Power Interface Management Specification previous to

revision 1.0.

Note:

The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be con-

figured by serial EEPROM. If enabled in the EEPROM the reset value of this register is 4000h. If not or if no EEPROM is

present, then the reset value is 000h.

Index 48h

Power Management and Control Status Register

This register implements the control and status of the PCI power management function. This register is available only if the PCICapabil-

ities bit (BAR1 Offset 00h[20]) is set in the nscControl register.

pmeStatus

Power Management Event Status: This bit is set when PME# is asserted.

Write 1 to clear. The PME# signal is also cleared when this is bit is written

to 1. A write of zero has no effect.

14:9

dynData

000000

Dynamic Power Consumption Data: This field reads 0 indicating that

dynamic data is not reported.

pmeEnab

R/W

Power Management Event Enable: When set, this bit enables the asser-

tion of PME#.

7:5

RSVD

---

000

Reserved

dynDataEnab

Dynamic Power Consumption Data: This bit reads 0 indicating that

dynamic data is not reported.

3:2

RSVD

---

Reserved

1:0

pwrState

R/W

Power State: This field is used to determine and set the CS4210 power

state.

00 = Current power state is D0

01 = Current power state is D1

10 = Current power state is D2

11 = Current power state is D3hot

Since D1 and D2 are not supported, a write of either 01 or 10 is treated as

the D0 state.

Note:

The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be con-

figured by serial EEPROM. If enabled in the EEPROM the reset value of this register is 8000h. If not or if no EEPROM is

present then the reset value is 000h.

Table 4-6. PCI Configuration Register Definitions

Bit

Name

Access

Reset

Description

CS4210 датащи(PDF) 46 Page - National Semiconductor (TI)

CS4210 датащи(HTML) 46 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL