CS4210 datasheet(63/102 Pages) NSC

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4.4.8

Global Unique ID Register

The Global Unique ID (GUID) (Table 4-17) is a 64-bit num-

ber that externally maps to the third and fourth quadlets of

the Bus_Info_Block. The GUID is contained in the two 32-

bit registers, GUIDHi and GUIDLo, BAR0+Offset 24h-28h.

The vendor ID is obtained from the IEEE Registration

Authority Committee (RAC). A company does not need to

obtain a vendor ID if it has been previously assign an IEEE

48-bit Globally Assigned Address Block or an IEEE-

assigned Organizationally Unique Identifier for use in net-

work applications.

4.4.9

Configuration ROM Mapping Register

The Configuration ROM Mapping register (Table 4-18) con-

tains the start address within system bus space that maps

to the start address of the 1394 configuration ROM for this

node. Only quadlet reads to the first 1 KB of the configura-

tion ROM map to system bus space, all other transactions

to this space are rejected with a 1394 “ack_type_error”.

Since the low order 10 bits of this address are reserved

andassumedtobezero, thesystem address forthe config-

urationROM must startona1KBboundary. Note that the

first five quadlets of the 1394 configuration ROM space are

mapped to the configuration ROM header and the

Bus_Info_Block, and so are handled directly by the

CS4210. This means that the first five quadlets addressed

by the configuration ROM mapping register are not used.

Software should ensure this address is valid before setting

HCControl.linkEnable (BAR0+Offset 50h[17]) to one.

Table 4-17. GUID Register

Bit

Name

Access

Reset

Description

BAR0+Offset 24h

GUIDHi Register

31:8

node_vendor_ID

Vendor ID Code: IEEE 1394 bus management field. Must be set by firm-

ware or hardware before the HCControl.linkEnable bit (BAR0+Offset

50h[17]) is set.

7:0

chip_ID_Hi

Chip Identification High: The upper 8 bits of the chip ID. IEEE 1394 bus

management field. Must be set by firmware or hardware before the HCCon-

trol.linkEnable bit (BAR0+Offset 50h[17]) is set.

BAR0+Offset 28h

GUIDLo Register

31:0

chip_ID_Lo

Chip Identification Low: The lower 32 bits of the chip ID. IEEE 1394 bus

management field. Must be set by firmware or hardware before the HCCon-

trol.linkEnable bit (BAR0+Offset 50h[17]) is set.

**The Global Unique ID (GUID) register is reset to 0 after a host power (hardware) reset. A value of 0 is an illegal value. This register is

not affected by a software reset. The GUID register is written only once after host power reset, by either:

1) an autonomous load operation from a local, un-modifiable such as the serial EEPROM or local parallel ROM, or

2) a single host write to each field performed only by firmware that is always executed on a hardware reset which affects the CS4210.

This firmware, as well as the GUID value that is loaded, may not be modifiable by any user action.

After one of these load mechanisms has executed, the GUID register is read-only.

Table 4-18. BAR0+Offset 34h: ConfigROMMap Register

Bit

Name

Access

Reset

Description

31:10

configROMaddr

Undef

Configuration ROM Address: If a quadlet read request to 1394 offset

FFFF_F000_0400h through offset FFFF_F000_07FFh is received, then the

low order 10 bits of the offset are added to this register to determine the

host memory address of the returned quadlet.

9:0

RSVD

Reserved

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