CS4210 datasheet(60/102 Pages) NSC

60 / 102 page

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4.4.4

Autonomous CSR Resources

The CS4210 implements a number of autonomous CSR

resources. In particular the 1394 compare-swap bus man-

agement registers are implemented in hardware, as is the

config ROM header, the Bus_Info_Block and access to the

first 1 KB of the configuration ROM. The DMA units handle

external 1394 bus requests to these resources automati-

cally. The serial bus registers shown in Table 4-12 manage

this function for the local host. 1394 requires certain 1394

bus management resource registers be accessible only via

“quadlet read” and “quadlet lock” (compare-and-swap)

transactions, otherwise ack_type_error is sent. These spe-

cial bus management resource registers are implemented

internal to the CS4210 to allow atomic compare-and-swap

access from either the host system or from the 1394 bus.

When these serial bus management resource registers are

accessed from the 1394 bus, the atomic compare-and-

swap transaction is autonomous, without software interven-

tion. If ack_complete is not received to end the transaction

for the generated lock response, IntEvent.lockRespErr

(refer to Table 4-26 on page 70) is triggered. To access

these bus management resource registers from the host,

the registers shown in Table 4-13 are used. To access

these bus management resource registers from the host

bus, first load the CSRReadData register with the new data

value to be loaded into the appropriate resource. Then load

the CSRCompareData register with the expected value.

Finally, write the CSRControl register with the selector

value of the resource. A write to the CSRControl register

initiates a compare-and-swap operation on the selected

resource. When the compare-and-swap operation is com-

plete, the CSRControl register csrDone bit is set, and the

CSRReadData register contains the value of the selected

resource prior to the host initiated compare-and-swap

operation. Note that an arbitrary update of these resources

cannot be done. Only compare-and-swap operations can

be used to modify the contents of these internal resource

registers.

Table4-12. Serial BusRegisters

CSR Address

csrSel Bits

(BAR0+Offset 14h[1:0]

Description

1394-1995

Section #

Reset (Hardware or

Bus Reset)

FFFF_F000_021Ch

BUS_MANAGER_ID

8.3.2.3.6

03Fh

FFFF_F000_0220h

BANDWIDTH_AVAILABLE

8.3.2.3.7

1333h

FFFF_F000_0224h

CHANNELS_AVAILABLE_HI

8.3.2.3.8

FFFF_FFFFh

FFFF_F000_0228h

CHANNELS_AVAILABLE_LO

8.3.2.3.8

FFFF_FFFFh

Table 4-13. CSR Registers

Bit

Name

Access

Reset

Description

BAR0+Offset 0Ch

CSRReadData Register

31:0

csrData

RWU

Undef

Control/Status Register Read Data: At start of operation, the data to be

stored if the compare is successful.

BAR0+Offset 10h

CSRCompareData Register

31:0

csrCompare

Undef

Control/Status Register Compare: The data to be compared with the

existing value of the CSR resource.

BAR0+Offset 14h

CSRControl Register

csrDone

Control/Status Register Done: This bit is set when a compare-swap oper-

ation is completed. It is reset whenever this register is written.

30:2

RSVD

Reserved

1:0

csrSel

Undef

Control/Status Register Resource Selection:

00 = BUS_MANAGER_ID

01 = BANDWIDTH_AVAILABLE

10 = CHANNELS_AVAILABLE_HI

11 = CHANNELS_AVAILABLE_LO

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