CS4210 datasheet(43/102 Pages) NSC

43 / 102 page

Revision 1.0

www.national.com

Index 06h

PCI Status Register

detectedParErr

R/W

Detected Parity Error: This bit is set whenever a parity error is detected.

Write 1 to clear.

signalSysErr

R/W

Signaled System Error: This bit is set whenever the CS4210 asserts

SERR# active.

Write 1 to clear.

recvMasterAbort

R/W

Received Master Abort: This bit is set whenever a master abort cycle

occurs while the CS4210 is the master for the PCI cycle.

Write 1 to clear.

recvTargeAbort

R/W

Received Target Abort: This bit is set whenever a target abort is received

while the CS4210 is the master for the PCI cycle.

Write 1 to clear.

signalTargetAbort

R/W

Signaled Target Abort: This bit is set whenever the CS4210 signals a tar-

get abort while it is the target for the PCI cycle.

Write 1 to clear.

10:9

devselTiming

DEVSEL# Timing: These bits are always 01, as the CS4210 always

responds to cycles for which it is an active target with medium DEVSEL#

timing: 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved

dataParityRep

R/W

Data Parity Detected: This bit is set when the CS4210 asserted PERR# or

observed PERR# asserted. The parityErrResp in the Command Register

(Index 04h[6]) must be enabled for this bit to function.

Write 1 to clear.

7:0

RSVD

Reserved

Index 08h

Revision Identification Register

7:0

revisionID

03h

Revision Identification: Specifies the silicon revision as 03h. This value

will be incremented for subsequent revisions.

Index 09h

PCI Class Code Register

23:16

Base Class

0Ch

Base Class: Identifies the device as being a serial bus controller.

15:8

Sub Class

00h

Sub Class: Identifies the device as being of IEEE 1394 class.

7:0

Programming

Interface

10h

Programming Interface: Identifies the device as being a 1394 OpenHCI

controller.

Index 0Ch

PCI Cache Line Size Register

7:0

cacheLineSize

00h

PCI Cache Line Size: This register sets the size of the PCI cache line. A

value of 00h indicates caching is disabled.

Index 0Dh

PCI Latency Timer Register

7:0

latencyTimer

R/W

50h

PCI Latency Timer Value: This register contains the maximum number of

PCI clocks that the CS4210 can hold ownership of the PCI bus as the bus

master. Bits [3:0] are a constant 0.

Index 0Eh

PCI Header Type Register

7:0

Header Type

00h

PCI Header Type Register: This register defines the format of this header.

This header is of type format 0. Additionally, bit 7 defines whether this PCI

device is a multi-function (bit 7 = 1) or single-function (bit 7 = 0) device.

Index 0Fh

PCI BIST Register

7:0

BIST

00h

PCI Built-In Self-Test: A value of 00h indicates no PCI controlled BIST.

Table 4-6. PCI Configuration Register Definitions

Bit

Name

Access

Reset

Description

CS4210 датащи(PDF) 43 Page - National Semiconductor (TI)

CS4210 датащи(HTML) 43 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL