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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS4210 датащи(PDF) 93 Page - National Semiconductor (TI) |
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CS4210 датащи(HTML) 93 Page - National Semiconductor (TI) |
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93 / 102 page  Revision 1.0 93 www.national.com Register Descriptions (Continued) 4.5.2 nscEventSet/Clear The nscEvent register (Table 4-59) contains events that are unique to the CS4210. This register is set (BAR1+Offset 04h) and clear (BAR1+Offset 08h). 4.5.3 nscMaskSet/Clear The nscEventMask register (Table 4-60) controls the masking of the nscEvent register. This register is set (BAR1+Offset 0Ch) and clear (BAR1+Offset 10h). Table 4-59. BAR1+Offset 04h (Set) and 08h (Clear): nscEvent Register Bit Name Access Reset Description 31:5 RSVD -- 0 Reserved 4 eepromAckErr RSCU Undef EEPROM Acknowledge Error: Set when an acknowledge is missing from the serial EEPROM load. 3 eepromCRCErr RSCU Undef EEPROM Cyclical Redundancy Check Error: Set when a CRC error occurs as a result of the serial EEPROM load. 2 physLockToggle RSCU Undef Physical Lock Toggle: Set when D15 of the nscPhysLockCount register (BAR1+Offset 48h) changes. 1 disableCmDetect RSCU Undef Disable Cycle Master Detector: Set when D15 of the nscPhysWriteCount register (BAR1+Offset 44h) changes. 0 noCycleMaster RSCU Undef No Cycle Master: Set when D15 of the nscPhysReadCount register (BAR1+Offset 40h) changes. Table 4-60. BAR1+Offset 0Ch (Set) and 10h (Clear): nscEventMask Register Bit Name Access Reset Description 31:5 RSVD -- 0 Reserved 4 eepromAckErrMask RSCU Undef EEPROM Acknowledge Error Mask: Set to 1 enables the corresponding bit in the nscEvent register (BAR1+Offset 04h). 3 eepromCRCErrMask RSC Undef EEPROM Cyclical Redundancy Check Error Mask: Set to 1 enables the corresponding bit in the nscEvent register (BAR1+Offset 04h). 2 physLockToggleMask RSC Undef Physical Lock Toggle Mask: Set to 1 enables the corresponding bit in the nscEvent register (BAR1+Offset 04h). 1 disableCmDetectMask RSC Undef Disable Cycle Master Detector Mask: Set to 1 enables the corresponding bit in the nscEvent register (BAR1+Offset 04h). 0 noCycleMasterMask RSC Undef No Cycle Master Mask: Set to 1 enables the corresponding bit in the nscEvent register (BAR1+Offset 04h). |
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