CS4210 datasheet(62/102 Pages) NSC

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Revision 1.0

4.4.7

Bus Options Register

The Bus Options register (Table 4-16) is a 32-bit number

that externally maps to the second quadlet of the

Bus_Info_Block.

This

written

locally

BAR0+Offset 20h. This register is loaded from the serial

EEPROM, if present, which sets the values after a hard-

ware reset.

Table 4-16. BAR0+Offset 20h: Bus Options Register

Bit

Name

Access

Reset

Description

31:27

irmc

Undef

Isochronous Resource Manager Capable: IEEE 1394 bus management

field. Must be valid at any time the HCControl.linkEnable bit (BAR0+Offset

50h[17]) is set.

cmc

Undef

Cycle Manager Capable: IEEE 1394 bus management bit. Must be valid at

any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.

isc

Undef

Isochronous Capable: IEEE 1394 bus management bit. Must be valid at

any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.

bmc

Undef

Bus Manager Capable: IEEE 1394 bus management bit. Must be valid at

any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.

pmc

Undef

Power Manager Capable: IEEE 1394 bus management bit. Must be valid

at any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.

26:24

RSVD

Reserved

23:16

cyc_clk_acc

Undef

Cycle Clock Access: IEEE 1394 bus management field. Must be valid at

any time the HCControl.linkEnable bit (BAR0+Offset 50h[17]) is set.

15:12

max_rec

Maximum Received: IEEE 1394 bus management field. Hardware initial-

izes max_rec to 1024 if no serial EEPROM is used or to the value stored for

this register in the EEPROM if present. Software may change max_rec,

however, this field must be valid at any time the HCControl.linkEnable bit

(BAR0+Offset 50h[17]) is set to 1. Note that received block write request

packets with a length greater than max_rec shall generate an

ack_type_error if the request is not handled by the physical response unit,

and may generate an ack_type_error otherwise.

** Reset values: For a hardware reset, max_rec is set 1024 or to the value

stored in the serial EEPROM, if present. For a soft reset, max_rec is not

changed.

11:8

RSVD

Reserved

7:6

Undef

Generation Counter: This field increments if any portion of configuration

ROM has changed since the prior bus reset.

5:3

RSVD

Reserved

2:0

link_spd

RWU

Link Speed: 000 = 100 Mbits/sec; 001 = 200 Mbits/sec; 010 = 400 Mbits/

sec; all other values are reserved.

**On a hardware reset, link_spd is set 010 (400 Mbits/sec) or to the value

stored in the serial EEPROM, if present. If the link_spd write protect in the

nscControl register (BAR1+Offset 00h[12]) is not set, software is permitted

to change link_spd to a lower value, which causes the link to reject packets

arriving at higher speeds.

**On a software reset, the value of link_spd is undefined.

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