CS4210 datasheet(48/102 Pages) NSC

48 / 102 page

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4.4

OHCI CONFIGURATION REGISTERS

The OHCI configuration registers are at the location speci-

fied by Base Address Register 0 (BAR0) in PCI configura-

tion space.

The registers must be accessed as 32-bit entities with host

processor quadlet reads or quadlet writes occurring on

quadlet boundaries. When HCControl.LPS is 0, the only

accessible registers are Version, VendorID, HCControl,

GUID_ROM, GUIDHi and GUIDLo. Access to all other reg-

isters is undefined until HCControl.LPS is set to 1.

All register fields are initialized to zero or their default value

upon power up. Reads of reserved fields yield undeter-

mined results. Unless specified, a 1394 bus reset will not

affect the register contents. The registers are either read/

write or set/clear registers. The read/write registers are

defined at a single location. The set/clear registers have

one location for setting bits in the register and a second

location for clearing those bits. When a value of 1 is written

to a set location, that value is taken as a bit mask to update

that bit. The other bits in the register are not changed.

Writing a 1 to a clear location sets that bit to zero and will

not change other bits. The register field descriptions in

Table 4-7 describe the operating modes of those registers.

Table 4-8 is a map for the registers accessed through

BAR0. Following this table are subsections providing

detailed information for each register.

Table 4-7. Operating Modes

Access

Tag

Name

Description

Read

Field may be read from the PCI bus.

Write

Field may be written from the PCI bus.

Update

Field may be autonomously updated

by the OHCI hardware.

Set

Field may be set from the PCI bus.

Clear

Field may be cleared from the PCI bus.

Table 4-8. OHCI Configuration Register Map/Summary: BAR0+Offset xxh

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

00h-03h

Version Register

RSVD

version

RSVD

revision

04h-07h

GUID_ROM Register

RSVD

rdData

RSVD

08h-0Bh

ATRetries Register

cycleLimit

(not implemented)

maxPhysResp-

Retries

RSVD

maxATResp-

Retries

maxATReq-

Retries

0Ch-0Fh

CSRCompareData Register

csrData

10h-13h

CSRCompareData Register

csrCompare

14h-17h

CSRControlRegister

RSVD

18h-1Bh

ConfigROMhdr Register

info_length

crc_length

rom_crc_value

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