CS4210 datasheet(40/102 Pages) NSC

40 / 102 page

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Revision 1.0

4.3

PCI CONFIGURATION REGISTERS

The PCI configuration space for the CS4210 is header type

0. Header type 0 is the format for the device’s configuration

header region which is the first 16 DWORDs of PCI config-

uration space. The configuration and operational registers

are memory mapped into PCI memory address space and

pointedtobyBaseAddress Registers(BARs) in thePCI

configuration space. PCI configuration space is not directly

memory or I/O mapped - its access is system dependent. A

software reset issued through the HCControl register does

not affect the contents of the PCI configuration space.

Table 4-5 is a map for the PCI Configuration Registers.

Table 4-6 gives detailed bit information.

Table 4-5. PCI Configuration Register Map: Index xxh

Index

Bits

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

76543210

00h-

03h

Device Identification Register

Vendor Identification Register

Device ID

Vendor ID

04h-

07h

Status Register

Command Register

devsel

Timing

RSVD

08h-

0Bh

PCI Device Class Code

Revision ID

Base Class

Sub Class

Programming Interface

revisionID

0Ch-

0Fh

PCI BIST Register

PCI Header Type

PCI Latency Timer

PCI Cache Line Size

BIST

Header Type

latencyTimer

cacheLineSize

10h-

13h

Base Address Register 0 - OHCI Configuration Registers

Base Address 0

RSVD

14h-

17h

Base Address Register 1 - National Specific Configuration Registers

Base Address 0

RSVD

18h-

2Bh

Reserved

2Ch-

2Fh

Subsystem ID

Subsystem Vendor ID

Subsystem ID

Subsys Vend ID

30h-

33h

Reserved

34h-

37h

Reserved

Capabilities

RSVD

Capabilities Pointer

38h-

3Bh

Reserved

3Ch-

3Fh

Max Latency

Min Grant

Interrupt Pin

Interrupt Line

Max Latency

Min Grant

Interrupt Pin

Interrupt Line

40h-

43h

Reserved

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