CS4210 datasheet(16/102 Pages) NSC

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Operational Description (Continued)

3.2

SOFTWARE INTERFACE OVERVIEW

There are three basic means by which software communi-

cates with the CS4210: registers, DMA, and interrupts.

3.2.1

Registers

The host architecture (PCI, for example) is responsible for

mapping the CS4210’s registers into a portion of the host’s

address space.

3.2.2

DMA Operation

DMA transfers in the CS4210 are accomplished through

one of two methods: DMA memory and physical response

DMA.

3.2.2.1

DMA Memory

DMA memory resident data structures are used to describe

lists of data buffers. The CS4210 automatically sequences

through this buffer descriptor list. This data structure also

contains status information regarding the transfers. Upon

completion of each data transfer, the DMA controller condi-

tionally updates the corresponding DMA context command

and conditionally interrupts the processor so it can observe

the status of the transaction. A set of registers within the

CS4210 is used to initialize each DMA context and to per-

form control actions such as starting the transfer.

3.2.2.2

Physical Response DMA

The CS4210 can be programmed to accept 1394 read and

write transactions as reads and writes to host memory

space. In this mode, the CS4210 acts as a bus bridge from

the 1394 bus into host memory. The formats for the data

sent and received in all these modes are specified in the

1394 Open Host Controller Interface Specification Release

1.00.

3.2.3

Interrupts

When any DMA transfer completes (or aborts), an interrupt

may be sent to the host system. In addition to the interrupt

sources which correspond to each DMA context comple-

tion, there is also a set of interrupts which correspond to

other CS4210 functions/units. For example, one of these

interrupts could be sent when a Self-ID packet stream has

been received. The processor interrupt line is controlled by

the IntEvent and IntMask registers. The IntEvent register

indicates which interrupt events have occurred, and the Int-

Mask register is used to enable selected interrupts. Soft-

ware writes to the IntEventClear register to clear interrupt

conditions in IntEvent. In addition, there are registers used

by the isochronous transmit and isochronous receive con-

trollers to indicate interrupt conditions for each context.

Table 3-3 shows a map of the IntEvent and IntMask Set/

Clear registers. Refer to Section 4.4.16.1 "IntEvent Regis-

ter" on page 70 and Section 4.4.16.3 "IntMask Register" on

page 72 for further information details.

3.2.3.1

Asynchronous Transmit Interrupts

Each asynchronous DMA context has one interrupt indica-

tion bit in the IntEvent register. For requests, it is the reqTx-

Complete bit and for responses it is the respTxComplete

bit. This interrupt indication bit is set to one if a completed

OUTPUT_LAST command has the “i” field set to 11b, or if

the “i” field is set to 01b and transmission of the packet did

not yield an ack_complete or an ack_pending.

3.2.3.2

Asynchronous Receive Interrupts

There are two interrupts for each context (request and

response) that software can use to gauge the usage of the

receivebuffers.Ifsoftwareneedstobeinformedofthe

arrival of each packet being sent to the context buffers, it

can use the RQPkt or RSPkt interrupts in the IntEvent reg-

ister. If software needs to be informed of the completion of

a buffer, it can set the descriptor i field to 11b, which trig-

gers either the ARRQ or ARRS interrupt in the IntEvent

Table 3-3. IntEvent and IntMask Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

BAR0+Offset 80h

IntEvent Set Register

BAR0+Offset 84h

IntEvent Clear Register

RSVD

BAR0+Offset 88h

IntMask Set Register

BAR0+Offset 8Ch

IntMask Clear Register

RSVD

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