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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VSC7440 датащи(PDF) 121 Page - Microsemi Corporation |
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VSC7440 датащи(HTML) 121 Page - Microsemi Corporation |
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121 / 444 page  Functional Descriptions VMDS-10492 VSC7440 Datasheet Revision 4.2 104 • Layer 2 and Layer 3 control protocol handling. Determines CPU forwarding, CPU extraction queue number, and dedicated protocol QoS handling. • Versatile Register Access Protocol (VRAP) handling. Extracts VRAP frames to VRAP engine. • Logical port mapping. Maps physical ingress port to logical port used by analyzer. The outcome of the classifier is the basic classification result, which can be overruled by more intelligent frame processing with VCAP classification matching (VCAP CLM). 3.16.1.1 VLAN Tag Extraction The following table lists the register associated with VLAN tag extraction. Up to five different VLAN tags are recognized by the device. • Customer tags (C-tags), which use TPID 0x8100. • Service tags (S-tags), which use TPID 0x88A8 (IEEE 802.1ad). • Service tags (S-tags), which use a custom TPID programmed in ANA_CL::VLAN_STAG_CFG. Three different custom TPIDs are supported. The device can parse and use information from up to three VLAN tags of any of the types previously described. Various blocks in the device use Layer 3 and Layer 4 information for classification and forwarding. Layer 3 and Layer 4 information can be extracted from a frame with up to three VLAN tags. Frames with more than three VLAN tags are always considered non-IP frames. 3.16.1.2 Pipeline Point Evaluation The basic classifier is active for all frames with no active pipeline information for frames injected before or at pipeline point ANA_CL and for frames extracted at or after pipeline point ANA_CL. Frames looped by the rewriter (PIPELINE_ACT = LBK_ASM) have their REW pipeline point changed to an ANA pipeline point, which indicates the point in the analyzer flow in ANA where they appear again after being looped. The following pipeline point translation are handled. • PIPELINE_PT = REW_PORT_VOE is changed to ANA_PORT_VOE • PIPELINE_PT = REW_OU_VOE is changed to ANA_OU_VOE • PIPELINE_PT = REW_IN_VOE is changed to ANA_IN_VOE • PIPELINE_PT = REW_SAT is changed to ANA_CLM • PIPELINE_PT = REW_OU_VOE is changed to ANA_OU_SW • PIPELINE_PT = REW_IN_SW is changed to ANA_IN_SW 3.16.1.3 Routing Tag Control The basic classifier determines which IP frames can be routed in terms of the VLAN tag types. If a frame can be routed, it is signalled to ANA_L3, where the routing decision is made. The following table lists the register associated with routing control. Table 66 • VLAN Tag Extraction Register Register Description Replication ANA_CL::VLAN_STAG_CFG Ethertype for S-tags in addition to default value 0x88A8. 3 Table 67 • Routing Tag Control Register Register Description Replication ANA_CL:PORT:VLAN_TPID_CTRL. BASIC_TPID_AWARE_DIS Configures valid TPIDs for routing. This configuration is shared with VLAN classification. Per port ANA_CL:PORT:VLAN_TPID_CTRL. RT_TAG_CTRL Configures number of valid VLAN tags in routable frames. Per port |
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