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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

165

VCAP IS2 contains 58 default actions that are allocated the following way:

•

0-52: Per ingress port default actions for first lookup.

•

53, 54: Per CPU port (CPU0 and CPU1) default actions for first lookup.

•

55, 56: Per virtual device (VD0 and VD1) default actions for first lookup.

•

57: Common default action for second lookup.

Each of the two VCAP IS2 actions (from first and second lookups) can be processed either at the pipeline

point ANA_OU_SW or at pipeline point ANA_IN_SW. This is controlled by VCAP IS2 action

IS_INNER_ACL. The order of processing is given as:

Process first action if the first’s action IS_INNER_ACL is 0.

Process second action if the second’s action IS_INNER_ACL is 0.

Process first action if the first’s action IS_INNER_ACL is 1.

Process second action if the second’s action IS_INNER_ACL is 1.

This implies that the second action can be processed in ANA_OU_SW pipeline point and the first action

can be processed in ANA_IN_SW pipeline point, or vice versa. Both actions can also be placed at the

same pipeline point in which case the first action is processed before the second.

Processing of each action obeys the frame’s current pipeline information (pipeline point and pipeline

action). For instance if the frame has been redirected at pipeline point ANA_CLM then neither of the

VCAP IS2 actions are applied. However, VCAP IS2 action IGNORE_PIPELINE_CTRL can overrule this.

Furthermore, frame processing between pipeline points ANA_OU_SW and ANA_IN_SW such as OAM

filtering or protection switching can influence the processing of the VCAP IS2 actions so that only an

action belonging to pipeline point ANA_OU_SW is processed.

The following table lists how the two VCAP IS2 action are combined when both VCAP IS2 actions are

processed. For most cases, the processing is sequential, meaning that if both actions have settings for

the same (for instance MIRROR_PROBE), the second processing takes precedence. Others are sticky

meaning they cannot be undone by the second processing if already set by the first.

Table 103 •

Combining VCAP IS2 Actions

Action name

Combining actions

IS_INNER_ACL

Processed individually for each action.

PIPELINE_FORCE_ENA

Processed individually for each action. Second processing uses the result from the first

processing which can prevent its processing if the pipeline information from first

processing disables the second processing.

PIPELINE_PT

See PIPELINE_FORCE_ENA.

HIT_ME_ONCE

Sticky.

INTR_ENA

Sticky.

CPU_COPY_ENA

Sticky.

CPU_QU_NUM

Sticky (each action can generate a CPU copy and based on configuration in

ANA_AC:PS_COMMON:CPU_CFG.ONE_CPU_COPY_ONLY_MASK, both copies can

be sent to CPU).

CPU_DIS

Processed individually for each action. Second processing may clear CPU copy from

first processing.

LRN_DIS

Sticky.

RT_DIS

Sticky.

POLICE_ENA

Sticky.

POLICE_IDX

Second action takes precedence when POLICE_ENA is set.

IGNORE_PIPELINE_CTRL Processed individually for each action.

LOG_MSG_INT

Second action takes precedence when LOG_MSG_INT > 0.

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