SC2200 datasheet(161/433 Pages) NSC

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Core Logic Module (Continued)

Figure 5-6. PCI Change to Sub-ISA and Back

5.2.6

AT Compatibility Logic

The Core Logic module integrates:

• Two 8237-equivalent DMA controllers with full 32-bit

addressing

• Two 8259A-equivalent interrupt controllers providing 13

individually programmable external interrupts

• An 8254-equivalent timer for refresh, timer, and speaker

logic

• NMI control and generation for PCI system errors and all

parity errors

• Support for standard AT keyboard controllers

• Positive decode for the AT I/O register space

• Reset control

5.2.6.1

DMA Controller

The Core Logic module supports industry standard DMA

architecture using two 8237-compatible DMA controllers in

cascaded configuration. The DMA functions supported by

the Core Logic module include:

• Standard seven-channel DMA support

• 32-bit address range support via high page registers

• IOCHRDY extended cycles for compatible timing trans-

fers

• Internal Sub-ISA bus master device support using

cascade mode

• NMI control and generation for PCI system errors and all

parity errors.

Note:

DMA interface signals are not available externally.

DMA Controllers

The Core Logic module supports seven DMA channels

using two standard 8237-equivalent controllers. DMA Con-

troller 1 contains Channels 0 through 3 and supports 8-bit

I/O adapters. These channels are used to transfer data

between 8-bit peripherals and PCI memory or 8/16-bit ISA

memory. Using the high and low page address registers, a

full 32-bit PCI address is output for each channel so they

can all transfer data throughout the entire 4 GB system

address space. Each channel can transfer data in 64 KB

pages.

DMA Controller 2 contains Channels 4 through 7. Channel

4isusedtocascade DMA Controller 1,soitisnot available

externally. Channels 5 through 7 support 16-bit I/O adapt-

ers to transfer data between 16-bit I/O adapters and 16-bit

system memory. Using the high and low page address reg-

isters, a full 32-bit PCI address is output for each channel

so they can all transfer data throughout the entire 4 GB

system address space. Each channel can transfer data in

128 KB pages. Channels 5, 6, and 7 transfer 16-bit

WORDs on even byte boundaries only.

DMA Transfer Modes

Each DMA channel can be programmed for

single, block,

demand or cascade transfer modes. In the most commonly

used mode,

single transfer mode, one DMA cycle occurs

per DRQ and the PCI bus is released after every cycle.

This allows the Core Logic module to timeshare the PCI

bus with the GX1 module. This is imperative, especially in

cases involving large data transfers, because the GX1

module gets locked out for too long.

FRAME#

TRDY#, IRDY#

GNT[x]

ROMCS#, DOCCS#,

PCI

Sub-ISA

TCS

TCP

DEVSEL#,STOP#

PAR,

PCI

AD[31:0],

C/BE[3:0]#

pull-up

IOCS0#, IOCS1#

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