SC2200 datasheet(160/433 Pages) NSC

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160

Revision 3.0

Core Logic Module (Continued)

5.2.5.6

ROM Interface

The Core Logic module positively decodes memory

addresses

000F0000h-000FFFFFh

(64

KB)

and

FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory

cycles cause the Core Logic module to claim the cycle, and

generate an ISA bus memory cycle with ROMCS#

asserted. The Core Logic module can also be configured to

respond to memory addresses FF000000h-FFFFFFFFh

(16 MB) and 000E0000h-000FFFFFh (128 KB).

8- or 16-bit wide ROM is supported. BOOT16 strap deter-

mines the width after reset. MCR[14,3] (Offset 34h) in the

General Configuration Block (see Table 3-2 on page 81 for

bit details) allows program control of the width.

Flash ROM is supported in the Core Logic module by

enabling the ROMCS# signal on write accesses to the

ROM region. Normally only read cycles are passed to the

ISA bus, and the ROMCS# signal is suppressed for write

cycles. When the ROM Write Enable bit (F0 Index 52h[1])

is set, a write access to the ROM address region causes a

writecycle to occurwithMEMW#,WR# andROMCS#

asserted.

5.2.5.7

PCI and Sub-ISA Signal Cycle Multiplexing

The SC2200 multiplexes most PCI and Sub-ISA signals on

the balls listed in Table 5-3, in order to reduce the number

of balls on the device. Cycle multiplexing is on a bus-cycle

by bus-cycle basis (see Figure 5-6 on page 161), where the

internal Core Logic PCI bridge arbitrates between PCI

cycles and Sub-ISA cycles. Other PCI and Sub-ISA signals

remain non-shared, however, some Sub-ISA signals may

be muxedwithGPIO.

Sub-ISA cycles are only generated as a result of GX1 mod-

ule accesses to the following addresses or conditions:

• ROMCS# address range.

• DOCCS# address range.

• IOCS0# address range.

• IOCS1# address range.

• An I/O writetoaddress 80hor to 84h.

• Internal ISA is programmed to be the subtractive decode

agent and no other agents claim the cycle.

If the Sub-ISA and PCI bus have more than four compo-

nents, the Sub-ISA components can be buffered using

74HCT245 or 74FCT245 type transceivers. The RD# (an

AND of IOR#, MEMR#) signal can be used as DIR control

while TRDE#is usedasenablecontrol.

Table 5-3. Cycle Multiplexed PCI / Sub-ISA Balls

PCI

Sub-ISA

Ball No.

EBGA

TEPBGA

AD0

A17

AD1

D16

AD2

A18

AD3

A15

AD4

A16

AD5

A14

AD6

C15

AD7

B14

AD8

C14

AD9

B13

AD10

A10

C13

AD11

A11

C12

AD12

A12

AD13

A13

C11

AD14

A14

A11

AD15

A15

B10

AD16

A16

AD17

A17

AD18

A18

AD19

A19

AD20

A20

AD21

A21

AD22

A22

AD23

A23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

C/BE0#

A13

C/BE1#

A10

C/BE2#

D10

C/BE3#

D11

PAR

D12

C10

TRDY#

D13

IRDY#

D14

STOP#

D15

DEVSEL#

BHE#

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