DP83916 datasheet(22/96 Pages) NSC

22 / 96 page

30 Buffer Management (Continued)

TXpktconfig to TXpktfrag

size (6 accesses) For the next

fragment if any it reads the next 3 fields from TXpktfrag

ptr0 to TXpktfrag

size (3 accesses) At the end of trans-

mission it writes the status information to TXpktstatus and

reads the TXpktlink field (2 accesses)

3532 Transmit Completion

The SONIC-16 stops transmitting under two conditions In

the normal case the SONIC-16 transmits the complete list

of descriptors in the TDA and stops after it detects EOL e

1 In the second case certain transmit errors cause the

SONIC-16 to abort transmission If

FIFO Underrun Byte

Count Mismatch Excessive Collision or Excessive Deferral

(if enabled) errors occur transmission ceases The CTDA

can also halt transmission under software control by setting

the HTX bit in the Command register Transmission halts

after the SONIC-16 writes to the TXpktstatus field

354 Dynamically Adding TDA Descriptors

Descriptors can be dynamically added during transmission

without halting the SONIC-16 The SONIC-16 can also be

guaranteed to transmit the complete list including newly ap-

pended descriptors (barring any transmit abort conditions)

by observing the following rule The last TXpktlink field

must point to the next location where a descriptor will be

added (see step 3 below and

Figure 3-15 ) The procedure

for appending descriptors consists of

1 Creating a new descriptor with its TXpktlink pointing to

the next vacant descriptor location and its EOL bit set to

a ‘‘1’’

2 Resetting the EOL bit to a ‘‘0’’ of the previously last de-

scriptor

3 Re-issuing the Transmit command (setting the TXP bit in

the Command register)

Step 3 assures that the SONIC-16 will transmit all the pack-

ets in the list If the SONIC-16 is currently transmitting the

Transmit command has no effect and continues transmitting

until it detects EOL e 1 If the SONIC-16 had just finished

transmitting it continues transmitting from where it had pre-

viously stopped

TLF11722 – 20

FIGURE 3-15 Initializing Last Link Field

40 SONIC-16 Registers

The SONIC-16 contains two sets of registers The status

control registers and the CAM memory cells The status

control registers are used to configure control and monitor

SONIC-16 operation They are directly addressable regis-

ters and occupy 64 consecutive address locations in the

system memory space (selected by the RA5 – RA0 address

pins) There are a total of 64 statuscontrol registers divided

into the following categories

User Registers

These registers are accessed by the user

to configure control and monitor SONIC-16 operation

These are the only SONIC-16 registers the user needs to

access

Figure 4-3 shows the programmer’s model and Ta-

ble 4-1 lists the attributes of each register

Internal Use Registers

These registers (Table 4-2) are

used by the SONIC-16 during normal operation and are not

intended to be accessed by the user

National Factory Test Registers

These registers (Table

4-3) are for National factory use only and should never be

accessed by the user Accessing these registers during nor-

mal operation can cause improper functioning of the

SONIC-16

41 THE CAM UNIT

The CAM unit memory cells are indirectly accessed by pro-

gramming the CAM descriptor area in system memory and

issuing the LCAM command (setting the LCAM bit in the

Control register) The CAM cells do not occupy address lo-

cations in register space and thus are not accessible

through the RA5 – RA0 address pins The CAM control regis-

ters however are part of the user register set and must be

initialized before issuing the LCAM command (see Section

4310)

The Content Addressable Memory (CAM) consists of six-

teen 48-bit entries for complete address filtering

(Figure 4-1)

of network packets Each entry corresponds to a 48-bit des-

tination address that is user programmable and can contain

any combination of Multicast or Physical addresses Each

entry is partitioned into three 16-bit CAM cells accessible

through CAM Address Ports (CAP 2 CAP 1 and CAP 0) with

CAP0 corresponding to the least significant 16 bits of the

Destination Address and CAP2 corresponding to the most

significant bits The CAM is accessed in a two step process

First the CAM Entry Pointer is loaded to point to one of the

16 entries Then each of the CAM Address Ports is ac-

cessed to select the CAM cell The 16 user programmable

CAM entries can be masked out with the CAM Enable regis-

ter (see section 4310)

Note

It is not necessary to program a broadcast address into the CAM

when it is desired to accept broadcast packets Instead to accept

broadcast packets set the BRD bit in the Receive Control register If

the BRD bit has been set the CAM is still active This means that it is

possible to accept broadcast packets at the same time as accepting

packets that match physical addresses in the CAM

411 The Load CAM Command

Because the SONIC-16 uses the CAM for a relatively long

period of time during reception it can only be written to via

the CAM Descriptor Area (CDA) and is only readable when

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