DP83916 datasheet(56/96 Pages) NSC

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50 Bus Interface (Continued)

545 Master Mode Bus Cycles

In order to add additional compatibility with different bus

architectures there are two other modes that affect the op-

eration of the bus These modes are called the synchronous

and asynchronous modes and are programmed by setting

or resetting the SBUS bit in the Data Configuration Register

(DCR) The synchronous and asynchronous modes do not

have an effect on slave accesses to the SONIC-16 but they

do affect the master mode operation Within the particular

busprocessor mode

synchronous and asynchronous

modes are very similar This section discusses all four

modes of operation of the SONIC-16 (NationalIntel vs Mo-

torola synchronous vs asynchronous) when it is a bus mas-

ter

In this section the rising edge of T1 and T2 means the

beginning of these states and the falling edge of T1 and T2

means the middle of these states

5451 Adding Wait States

To accommodate different memory speeds the SONIC-16

provides two methods for adding wait states for its bus op-

erations Both of these methods can be used singly or in

conjunction with each other A memory cycle is extended by

adding additional T2 states The first method inserts wait-

states by withholding the assertion of DSACK01 STERM or

RDYi The other method allows software to program wait-

states Programming the WC0 WC1 bits in the Data Config-

uration Register allows 1 to 3 wait-states to be added on

each memory cycle These wait states are inserted between

the T1 and T2 bus states and are called T2(wait) bus states

The SONIC-16 will not look at the DSACK01 STERM or

RDYi lines until the programmed wait states have passed

Hence in order to complete a bus operation that includes

programmed wait states the DSACK01 STERM or RDYi

lines must be asserted at their proper times at the end of the

cycle during the last T2 not during a programmed wait

state The only exception to this is asynchronous mode

where DSACK01 or RDYi would be asserted during the last

programmed wait state T2 (wait) See the timing for these

signals in the timing diagrams for more specific information

Programmed wait states do not affect Slave Mode bus cy-

cles

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