DP83916 datasheet(77/96 Pages) NSC

77 / 96 page

70 AC and DC Specifications (Continued)

MEMORY READ BMODE e 0 ASYNCHRONOUS MODE

TLF11722 – 64

Number

Parameter

20 MHz

Units

Min

Max

BSCK to Address Valid

T10

Address Hold Time from BSCK

T11b

BSCK to ADS DS ECS Low

T12b

BSCK to ADS DS ECS High

T13

BSCK to DS High

T15

ADS High Width (Note 2)

bcyc b 5ns

T16

Read Data Strobe High Width (Note 2)

bcyc b 12

T17

Read Data Strobe Low Width (Note 2)

bcyc b 5ns

T23

Read Data Setup Time to BSCK

T24

Read Data Hold Time from BSCK

T28

BSCK to MWR (Read) Valid (Note 1)

T32a

Ready Asynch Setup Time to BSCK (Note 3)

T33a

Ready Asynch Hold Time to BSCK

Note 1

For successive read operations MWR remains low and for successive write operations MWR remains high During RBA and TBA transfers the MWR

signal will stay either high or low for the entire burst of the transfer During RDA and TDA transfers the MWR signal will switch on the rising edge of a Ti (idle) state

that is inserted between the read and the write operation

Note 2

bcyc e bus clock cycle time (T3)

Note 3

This setup time assures that the SONIC-16 terminates the memory cycle on the next bus clock (BSCK) RDYi does not need to be synchronized to the bus

clock though since it is an asynchronous input in this case RDYi is sampled during the falling edge of BSCK If the SONIC-16 samples RDYi low during the T1

cycle the SONIC-16 will finish the current access in a total of two bus clocks instead of three which would be the case if RDYi had been sampled low during

T2(wait) (This is assuming that programmable wait states are set to 0)

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