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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83916 датащи(PDF) 94 Page - National Semiconductor (TI) |
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DP83916 датащи(HTML) 94 Page - National Semiconductor (TI) |
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94 / 96 page  80 AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken to be at the AUI side of the pulse transformer Input Pulse Levels (TTLCMOS) GND to 30V Input Rise and Fall Times (TTLCMOS) 5 ns Input and Output Reference Levels (TTLCMOS) 15V Input Pulse Levels (Diff) b 350 mV to b1315 mV Input and Output 50% Point of Reference Levels (Diff) the Differential TRI-STATE Reference Levels Float (DV) g05V OUTPUT LOAD (See Figure below) TLF11722 – 83 Note 1 50 pF includes scope and jig capacitance Note 2 S1 e Open for timing tests for push pull outputs S1 e VCC for VOL test S1 e GND for VOH test S1 e VCC for High Impedance to active low and active low to High Impedance measurements S1 e GND for High Impedance to active high and active High to High Impedance measurements PIN CAPACITANCE TA e 25 C f e 1 MHz Symbol Parameter Typ Units CIN Input Capacitance 7 pF COUT Output Capacitance 7 pF DERATING FACTOR Output timing is measured with a purely capacitive load of 50 pF The following correction factor can be used for other loads CL t 50 pF a 005 nspF AUI Transmit Test Load TLF11722 – 84 Note In the above diagram the TXa and TXb signals are taken from the AUI side of the isolation (pulse transformer) The pulse transformer used for all testing is a selected 100 mH g01% Pulse Engineering PE64103 94 |
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