DP83916 datasheet(27/96 Pages) NSC

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40 SONIC-16 Registers (Continued)

43 REGISTER DESCRIPTION

431 Command Register

(RAk50le0h)

This register

(Figure 4-4 ) is used for issuing commands to the SONIC-16 These commands are issued by setting the corre-

sponding bits for the function For all bits except for the RST bit the SONIC-16 resets the bit after the command is completed

With the exception of RST writing a ‘‘0’’ to any bit has no effect Before any commands can be issued the RST bit must first be

reset to ‘‘0’’ This means that if the RST bit is set two writes to the Command Register are required to issue a command to the

SONIC-16 one to clear the RST bit and one to issue the command

This register also controls the general purpose 32-bit Watchdog Timer After the Watchdog Timer register has been loaded it

begins to decrement once the ST bit has been set to ‘‘1’’ An interrupt is issued when the count reaches zero if the Timer

Complete interrupt is enabled in the IMR

During hardware reset bits 7 4 and 2 are set to a ‘‘1’’ all others are cleared During software reset bits 9 8 1 and 0 are

cleared and bits 7 and 2 are set to a ‘‘1’’ all others are unaffected

9876543

000000

LCAM RRRA RST

STP

RXEN RXDIS

TXP

HTX

reread only rwereadwrite

FIGURE 4-4 Command Register

Field

Meaning

LCAM

LOAD CAM

RRRA

READ RRA

RST

SOFTWARE RESET

START TIMER

STP

STOP TIMER

RXEN

RECEIVER ENABLE

RXDIS

RECEIVER DISABLE

TXP

TRANSMIT PACKET(S)

HTX

HALT TRANSMISSION

Bit

Description

15 – 10

Must be 0

LCAM LOAD CAM

Setting this bit causes the SONIC-16 to load the CAM with the descriptor that is pointed to by the CAM Descriptor

Pointer register

Note

This bit must not be set during transmission (TXP is set) The SONIC-16 will lock up if both bits are set simultaneously

RRRA READ RRA

Setting this bit causes the SONIC-16 to read the next RRA descriptor pointed to by the Resource Read Pointer

(RRP) register Generally this bit is only set during initialization Setting this bit during normal operation can cause

improper receive operation

RST SOFTWARE RESET

Setting this bit resets all internal state machines The CRC generator is disabled and the Tally counters are halted

but not cleared The SONIC-16 becomes operational when this bit is reset to ‘‘0’’ A hardware reset sets this bit to a

‘‘1’’ It must be reset to ‘‘0’’ before the SONIC-16 becomes operational

Must be 0

ST START TIMER

Setting this bit enables the general-purpose watchdog timer to begin counting or to resume counting after it has

been halted This bit is reset when the timer is halted (ie STP is set) Setting this bit resets STP

STP STOP TIMER

Setting this bit halts the general-purpose watchdog timer and resets the ST bit The timer resumes when the ST bit is

set This bit powers up as a ‘‘1’’ Note Simultaneously setting bits ST and STP stops the timer

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