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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83916 датащи(PDF) 62 Page - National Semiconductor (TI) |
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DP83916 датащи(HTML) 62 Page - National Semiconductor (TI) |
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62 / 96 page  50 Bus Interface (Continued) During read cycles ( Figures 5-16 and 5-17 ) data (D15 – D0) is latched at the falling edge of T2 and DS is asserted at the falling edge of T1 For write cycles ( Figures 5-18 and 5-19 ) data is driven on the falling edge of T1 If there are wait states inserted DS is asserted on the falling edge of the first T2(wait) DS is not asserted for zero wait state write cycles The SONIC-16 terminates the memory cycle by deasserting DS at the falling edge of T2 Note If the setup time for RDYi is met during T1 the full asynchronous bus cycle will take only 2 bus clocks This may be an unwanted situation If so RDYi should be deasserted during T1 TLF11722 – 44 FIGURE 5-18 Memory Write BMODEe0 Asynchronous (1 Wait-State) TLF11722 – 45 FIGURE 5-19 Memory Write BMODEe0 Asynchronous (2 Wait-State) 62 |
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