DP83916 datasheet(85/96 Pages) NSC

85 / 96 page

70 AC and DC Specifications (Continued)

MEMORY ARBITRATIONSLAVE ACCESS

TLF11722 – 72

Number

Parameter

20 MHz

Units

Min

Max

T56

CS Low Asynch Setup to BSCK

(Note 2)

T57

CS High Asynch Setup to BSCK

T58

MREQ Low Asynch Setup to BSCK

(Note 2)

T59

MREQ High Asynch Setup to BSCK

T60

MREQ or CS to SMACK Low (Notes 3 4)

bcyc

T80

MREQ to SMACK High

T81

BSCK to SMACK Low

Note 1

Both CS and MREQ must not be asserted concurrently If these signals are successively asserted there must be at least two bus clocks between the

deasserting and asserting edges of these signals

Note 2

It is not necessary to meet the setup times for MREQ or CS since these signals are asynchronously sampled Meeting the setup time for these signals

however makes it possible to use T60 to determine exactly when SMACK will be asserted

Note 3

The smaller value for T60 refers to when the SONIC-16 is accessed during an Idle condition and the other value refers to when the SONIC-16 is accessed

during non-idle conditions These values are not tested but are guaranteed by design This specification assumes that CS or MREQ is asserted

bus clock before

the falling edge that these signals are asynchronously clocked in on (see T56 and T58) If T56 is met for CS or T58 is met for MREQ then SMACK will be asserted

exactly 1 bus clock when the SONIC-16 was idle or 5 bus clocks when the SONIC-16 was in master mode after the edge that T56 and T58 refer to (This is

assuming that there were no wait states in the current master mode access Wait states will increase the time for SMACK to go low by the number of wait states in

the cycle) SAS must have been asserted for this timing to be correct See SAS and CS timing in the Register Read and Register Write timing specifications

Note 4

bcyc e bus clock cycle time (T3)

Note 5

The way in which SMACK is asserted is due to CS is not the same as the way in which SMACK is asserted due to MREQ SMACK goes low as a direct

result of the assertion of MREQ whereas for CS SAS must also be driven low (BMODE e 1) or high (BMODE e 0) before SMACK will be asserted This means

that when SMACK is asserted due to MREQ SMACK will remain asserted until MREQ is deasserted Multiple memory accesses can be made to the shared

memory without SMACK ever going high When SMACK is asserted due to CS however SMACK will only remain low as long as SAS is also low (BMODE e 1) or

high (BMODE e 0) SMACK will not remain low throughout multiple register accesses to the SONIC-16 because SAS must toggle for each register access This is

an important difference to consider when designing shared memory designs

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