DP83916 datasheet(63/96 Pages) NSC

63 / 96 page

50 Bus Interface (Continued)

546 Bus Exceptions (Bus Retry)

The SONIC-16 provides the capability of handling errors

during the execution of the bus cycle (

Figure 5-20 )

The system asserts BRT (bus retry) to force the SONIC-16

to repeat the current memory cycle When the SONIC-16

detects the assertion of BRT it completes the memory cy-

cle at the end of T2 and gets off the bus by deasserting

BGACK or HOLD Then if Latched Bus Retry mode is not

set (LBR in the Data Configuration Register Section 432)

the SONIC-16 requests the bus again to retry the same

memory cycle If Latched Bus Retry is set though the SON-

IC-16 will not retry until the BR bit in the ISR (see Section

436) has been reset and BRT is deasserted BRT has

precedence of terminating a memory cycle over DSACK01

STERM or RDYi

BRT may be sampled synchronously or asynchronously by

setting the EXBUS bit in the DCR (see Section 432) If

synchronous Bus Retry is set BRT is sampled on the rising

edge of T2 If asynchronous Bus Retry is set BRT is double

synchronized from the falling edge of T1 The asynchronous

setup time does not need to be met but doing so will guar-

antee that the bus exception will occur in the current bus

cycle instead of the next bus cycle Asynchronous Bus Re-

try may only be used when the SONIC-16 is set to asynchro-

nous mode

Note 1

The deassertion edge of HOLD is dependent on the PH bit in the

DCR2 (see Section 437) Also BGACK is driven high for about

bus clock before going TRI-STATE

Note 2

If Latched Bus retry is set BRT need only satisfy its setup time (the

hold time is not important) Otherwise BRT must remain asserted

until after the Th state

Note 3

If DSACK01 STERM or RDYi remain asserted after BRT the next

memory cycle may be adversely affected

547 Slave Mode Bus Cycle

The SONIC-16’s internal registers can be accessed by one

of two methods (BMODE e 1 or BMODE e 0) In both

methods the SONIC-16 is a slave on the bus This section

describes the SONIC-16’s slave mode bus operations

5471 Slave Cycle for BMODE e 1

The system accesses the SONIC-16 by driving SAS SRW

and RAk50l These signals will be sampled each bus cy-

cle but the SONIC-16 will not actually start a slave cycle

until CS has also been asserted CS should not be asserted

before SAS is driven low as this will cause improper slave

operation Once SAS has been driven low between one

and two bus clocks after the assertion of CS SMACK will be

asserted to signify that the SONIC-16 has started the slave

cycle Although CS is an asynchronous input meeting its

setup time (as shown in

Figures 5-21 and 5-22 ) will guaran-

tee that SMACK which is asserted off of a falling edge will

be asserted 1 bus clock after the falling edge that CS is

clocked in on This is assuming that the SONIC-16 is not a

bus master when CS was asserted If the SONIC-16 is a bus

master then when CS is asserted the SONIC-16 will com-

plete its current master bus cycle and get off the bus tempo-

rarily (see Section 548) In this case SMACK will be as-

serted 5 bus clocks after the falling edge that CS was

clocked in on This is assuming that there were no wait

states in the current master mode access Wait states will

increase the time for SMACK to go low by the number of

wait states in the cycle

If the slave access is a read cycle (

Figure 5-21 ) then the

data will be driven off the same edge as SMACK Ifitisa

write cycle (

Figure 5-22 ) then the data will be latched in

exactly 2 bus clocks after the assertion of SMACK In either

case DSACK01 are driven low 2 bus clocks after SMACK

to terminate the slave cycle For a read cycle the assertion

of DSACK01 indicates valid register data and for a write

cycle

the assertion indicates that the SONIC-16 has

latched the data The SONIC-16 deasserts DSACK01

SMACK and the data if the cycle is a read cycle at the rising

edge of SAS or CS depending on which is deasserted first

Note 1

Although the SONIC-16 responds as a 32-bit peripheral when it

drives DSACK01 low it transfers data only on lines Dk150l

Note 2

For multiple register accesses CS can be held low and SAS can be

used to delimit the slave cycle (this is the only case where CS may

be asserted before SAS) In this case SMACK will be driven low

due to SAS going low since CS has already been asserted Notice

that this means SMACK will not stay asserted low during the entire

time CS is low (as is the case for MREQ Section 548)

Note 3

If memory request (MREQ) follows a chip select (CS) it must be

asserted at least 2 bus clocks after CS is deasserted Both CS and

MREQ must not be asserted concurrently

Note 4

When CS is deasserted it must remain deasserted for at least one

bus clock

Note 5

The way in which SMACK is asserted due to CS is not the same as

the way in which SMACK is asserted due to MREQ The assertion

of SMACK is dependent upon both CS and SAS being low not just

CS This is not the same as the case for MREQ (see Section 548)

The assertion of SMACK in these two cases should not be con-

fused

TLF11722 – 46

FIGURE 5-20 Bus Exception (Bus Retry)

DP83916 датащи(PDF) 63 Page - National Semiconductor (TI)

DP83916 датащи(HTML) 63 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL