DP83916 datasheet(70/96 Pages) NSC

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60 Network Interfacing (Continued)

External ENDEC

When EXTe1 the internal ENDEC is by-

passed and the signals are provided directly to the user

Since SONIC-16’s on-chip ENDEC is the same as Nation-

al’s DP83910 Serial Network Interface (SNI) the interface

considerations discussed in this section would also apply to

using this device in the external ENDEC mode

61 MANCHESTER ENCODER AND

DIFFERENTIAL DRIVER

The ENDEC unit’s encoder begins operation when the MAC

section begins sending the serial data stream It converts

NRZ data from the MAC section to Manchester data for the

differential drivers (TXa b) In Manchester encoding the

first half of the bit cell contains the complementary data and

the second half contains the true data

(Figure 6-3) A tran-

sition always occurs at the middle of the bit cell As long as

the MAC continues sending data the ENDEC section re-

mains in operation At the end of transmission the last tran-

sition is always positive occurring at the center of the bit

cell if the last bit is a one or at the end of the bit cell if the

last bit is a zero

The differential transmit pair drives up to 50 meters of twist-

ed pair AUI cable These outputs are source followers which

require two 270X pull-down resistors to ground In addition

a pulse transformer is required between the transmit pair

output and the AUI interface

The driver allows both half-step and full-step modes for

compatibility with Ethernet I and IEEE 8023 When the SEL

pin is tied to ground (for Ethernet I) TXa is positive with

respect to TXb during idle on the primary side of the isola-

tion transformer (

Figure 6-2 ) When SEL is tied to VCC (for

IEEE 8023) TXa and TXb are equal in the idle state

TLF11722 – 54

FIGURE 63 Manchester Encoded Data Stream

611 Manchester Decoder

The decoder consists of a differential receiver and a phase

lock loop (PLL) to separate the Manchester encoded data

stream into clock signals and NRZ data The differential in-

put must be externally terminated with two 39X resistors

connected in series In addition

a pulse transformer is re-

quired between the receive input pair and the AUI interface

To prevent noise from falsely triggering the decoder a

squelch circuit at the input rejects signals with a magnitude

less than b175 mV Signals more negative than b300 mV

are decoded

Once the input exceeds the squelch requirements the de-

coder begins operation The decoder may tolerate bit jitter

up to 18 ns in the received data The decoder detects the

end of a frame within one and a half bit times after the last

bit of data

612 Collision Translator

When the Ethernet transceiver (DP8392 CTI) detects a colli-

sion it generates a 10 MHz signal to the differential collision

inputs (CDa and CDb) of the SONIC-16 When SONIC-16

detects these inputs active its Collision translator converts

the 10 MHz signal to an active collision signal to the MAC

section This signal causes SONIC-16 to abort its current

transmission and reschedule another transmission attempt

The collision differential inputs are terminated the same way

as the differential receive inputs and a pulse transformer is

required between the collision input pair and the AUI inter-

face The squelch circuitry is also similar rejecting pulses

with magnitudes less than b175 mV

613 Oscillator Inputs

The oscillator inputs to the SONIC-16 (X1 and X2) can be

driven with a parallel resonant crystal or an external clock

In either case the oscillator inputs must be driven with a

20 MHZ signal The signal is divided by 2 to generate the

10 MHz transmit clock (TXC) for the MAC unit The oscilla-

tor also provides internal clock signals for the encoding and

decoding circuits

6131 External Crystal

According to the IEEE 8023 standard the transmit clock

(TXC) must be accurate to 001% This means that the os-

cillator circuit which includes the crystal and other parts

involved must be accurate to 001% after the clock has

been divided in half Hence when using a crystal it is nec-

essary to consider all aspects of the crystal circuit An ex-

ample of a recommended crystal circuit is shown in

Figure

6-4 and suggested oscillator specifications are shown in Ta-

ble 6-1 The load capacitors in

Figure 6-4 C1 and C2

should be no greater than 36 pF each including all stray

capacitance (see note 2 below) The resistor R1 may be

required in order to minimize frequency drift due to changes

in VCC If R1 is required its value must be carefully selected

since R1 decreases the loop gain If R1 is made too large

the loop gain will be greatly reduced and the crystal will not

oscillate If R1 is made too small normal variations in VCC

may cause the oscillation frequency to drift out of specifica-

tion As a first rule of thumb the value of R1 should be

made equal to five times the motional resistance of the crys-

tal The motional resistance of 20 MHz crystals is usually in

the range of 10X to 30X This implies that reasonable val-

ues for R1 should be in the range of 50X to 150X The

decision of whether or not to include R1 should be based

upon measured variations of crystal frequency as each of

the circuit parameters are varied

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