DP83916 datasheet(88/96 Pages) NSC

88 / 96 page

70 AC and DC Specifications (Continued)

(Note 1)

TLF11722 – 75

Number

Parameter

20 MHz

Units

Min

Max

T56

CS Asynch Setup to BSCK (Note 5)

T60

MREQ or CS to SMACK Low (Notes 4 6 9)

bcyc

T62

SAS Assertion before CS (Note 7)

T63

T64

T67

SRW (Read) Setup to SAS

0ns

T72a

SMACK to DSACK01 Low (Notes 4 9)

bcyc

T74

SRW (Read) Hold from SAS

T75a

BSCK to DSACK01 Low

T77

CS to DSACK01 High (Notes 2 3)

T77a

SAS to DSACK01 High (Notes 2 3)

T78

Skew between DSACK01

T79a

BSCK to SMACK High

T81

BSCK to SMACK Low

T82

BSCK to Register Data Valid

T85a

Min CS Deassert Time (Note 4)

bcyc

T86

SAS or CS to Register Data TRI-STATE

(Notes 2 8)

Note 1

This figure shows a slave access to the SONIC-16 when the SONIC-16 is idle or rather not in master mode If the SONIC-16 is a bus master there will be

some differences as noted in the Memory ArbitrationSlave Access diagram The BSCK states (T1 T2 etc) are the equivalent processor states during a slave

access

Note 2

If CS is deasserted before the rising edge of SAS T77 and T86 are referenced off the rising edge of CS instead of SAS

Note 3

DSACK01 are driven high for about

bus clock before going TRI-STATE

Note 4

bcyc e bus clock cycle time (T3)

Note 5

It is not necessary to meet the setup time for CS since this signal is asynchronously sampled Meeting the setup time for this signal however makes it

possible to use T60 to determine exactly when SMACK will be asserted

Note 6

The smaller value for T60 refers to when the SONIC-16 is accessed during an Idle condition and the other value refers to when the SONIC-16 is accessed

during non-idle conditions These values are not tested but are guaranteed by design This specification assumes that CS is asserted

bus clock before the

falling edge that CS is asynchronously clocked in on (see T56) If T56 is met for CS then SMACK will be asserted exactly 1 bus clock when the SONIC-16 was idle

or 5 bus clocks when the SONIC-16 was in master mode after the edge that T56 refers to (This is assuming that there were no wait states in the current master

mode access Wait states will increase the time for SMACK to go low by the number of wait states in the cycle)

Note 7

SAS may be asserted at anytime before or simultaneous to the falling edge of CS

Note 8

This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns eariler enabling other devices to drive

these lines without contention

Note 9

These values are not tested but are guaranteed by design They are provided as in design guideline only

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