DP83916 datasheet(49/96 Pages) NSC

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50 Bus Interface (Continued)

TABLE 5-1 Pin Description

(Continued)

Symbol

Driver

Direction

Description

Type

BUS INTERFACE PINS

(Continued)

Chip Select

The system asserts this pin low to access the SONIC-16’s registers The

registers are selected by placing an address on lines RA5 – RA0

Note

Both CS and MREQ must not be asserted concurrently If these signals are

successively asserted there must be at least two bus clocks between the deasserting

edge of the first signal and the asserting edge of the second signal

SAS

Slave Address Strobe

The system asserts this pin to latch the register address on

lines RA0 – RA5 When BMODE e 1 the address is latched on the falling edge of SAS

When BMODE e 0 the address is latched on the rising edge of SAS

SDS

Slave Data Strobe

The system asserts this pin to indicate valid data is on the bus

during a register write operation or when data may be driven onto the bus during a

SRW

The system asserts this pin to indicate whether it will read from or write to the SONIC-

16’s registers

SWR

Slave ReadWrite (SRW)

When BMODE e 1 this signal is asserted high during a

read and low during a write

Slave ReadWrite Strobe (SWR)

when BMODE e 0 this signal is asserted low during

a read and high during a write

TRI

O Z

Data Strobe

When the SONIC-16 is bus master it drives this pin low during a read

cycle to indicate that the slave device may drive data onto the bus in a write cycle this

pin indicates that the SONIC-16 has placed valid data onto the bus

DSACK0

TRI

I O Z

Data and Size Acknowledge 0 and 1

(DSACK01 BMODE e 1) These pins are the

output slave acknowledge to the system when the SONIC-16 registers have been

RDYi

accessed and the input slave acknowledgement when the SONIC-16 is busmaster

DSACK1

TRI

I O Z

When a register has been accessed the SONIC-16 drives the DSACK01 pins low to

RDYo

TRI

O Z

terminate the slave cycle (Note that the SONIC-16 responds as a 32-bit peripheral but

drives data only on lines D0 – D15) When the SONIC-16 is bus master it samples these

pins before terminating its memory cycle These pins are sampled synchronously or

asynchronously depending on the state of the SBUS bit in the Data Configuration

bus sizing

Ready Input

(RDYi BMODE e 0) When the SONIC-16 is a bus master the system

asserts this signal high to insert wait-states and low to terminate the memory cycle This

signal is sampled synchronously or asynchronously depending on the state of the SBUS

bit See Sections 545 and 432 for details

Ready Output

(RDYo BMODE e 0) When a register is accessed the SONIC-16

asserts this signal to terminate the slave cycle

BRT

Bus Retry

When the SONIC-16 is bus master the system asserts this signal to rectify a

potentially correctable bus error This pin has 2 modes Mode 1 (the LBR in the Data

Configuration register is set to 0) Assertion of this pin forces the SONIC-16 to terminate

the current bus cycle and will repeat the same cycle after BRT has been deasserted

Mode 2 (the LBR bit in the Data Configuration register is set to 1) Assertion of this

signal forces the SONIC-16 to retry the bus operation as in Mode 1 However the

SONIC-16 will not continue DMA operations until the BR bit in the ISR is reset

ECS

TRI

O Z

Early Cycle Start

This output gives the system earliest indication that a memory

operation is occurring This signal is driven low at the rising edge of T1 and high at the

falling edge of T1

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