DP83916 datasheet(81/96 Pages) NSC

81 / 96 page

70 AC and DC Specifications (Continued)

MEMORY READ BMODE e 1 ASYNCHRONOUS MODE

TLF11722 – 68

Number

Parameter

20 MHz

Units

Min

Max

BSCK to Address Valid

T10

Address Hold Time from BSCK

T11a

BSCK to AS DS ECS Low

T12a

BSCK to AS ECS High

T13a

BSCK to DS High

T14

AS Strobe Low Width (Note 3)

bcyc b 7ns

T15a

AS Strobe High Width (Note 3)

bcyc b 15

T16

Read Data Strobe High Width (Note 3)

bcyc b 12

T17

Read Data Strobe Low Width (Note 3)

bcyc b 5ns

T22

Address Valid to AS (Note 3)

bch b 18

T23a

Read Data Setup Time to BSCK

T24a

Read Data Hold Time from BSCK

T28

BSCK to MRW (Read) Valid (Note 1)

T30

DSACK01 Setup to BSCK (Note 2)

T30a

STERM Setup to BSCK (Note 2)

T31

DSACK01 Hold from BSCK

T31a

STERM Hold from BSCK

Note 1

For successive write operations MRW remains low

Note 2

Meeting the setup time for DSACK01 or STERM guarantees that the SONIC-16 will terminate the memory cycle 1

bus clocks after DSACK01 were

sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK01 or STERM are sampled properly in a low state If the SONIC-16 samples

DSACK01 or STERM low during the T1 or first T2 state respectively the SONIC-16 will finish the current access in a total of two bus clocks instead of three

(assuming that programmable wait states are set to 0) DSACK01 are asynchronously sampled and STERM is synchronously sampled

Note 3

bcyc e bus clock cycle time (T3) bch e bus clock high time (T2)

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