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DP83916 датащи(PDF) 46 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали DP83916
подробное описание детали  SONICTM-16 Systems-Oriented Network Interface Controller
PDF  96 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83916 датащи(HTML) 46 Page - National Semiconductor (TI)

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50 Bus Interface (Continued)
TABLE 5-1 Pin Description
(Continued)
Symbol
Driver
Direction
Description
Type
NETWORK INTERFACE PINS
(Continued)
RXDo
TP
O
This pin will be TRI-STATE until the DCR has been written to (See section 432
EXBUS for more information)
RXDi
I
Receive Data Output (RXDo)
from the internal ENDEC (EXT e 0) NRZ data output
EXUSR0
TRI
O Z
When EXT e 0 the RXDOUT signal is internally connected between the ENDEC and
MAC units This signal must be sampled on the rising edge of the receive clock output
(RXCo) Although this signal is used internally by the SONIC-16 it is also provided as an
output to the user
Receive Data Input (RXDi)
from an external ENDEC (EXT e 1) The NRZ data
decoded from the external ENDEC This data is clocked in on the rising edge of RXCi
Extended User Output (EXUSR0)
When EXBUS has been set (see section 432) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC-16
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 437)
RXCo
TP
O
This pin will be TRI-STATE until the DCR has been written to (See section 432
EXBUS for more information)
RXCi
I
Receive Clock Output (RXCo)
from the internal ENDEC (EXT e 0) When EXT e 0
EXUSR1
TRI
O Z
the RXCo signal is internally connected between the ENDEC and MAC units This signal
is the separated receive clock from the Manchester data stream It remains active 5-bit
times after the deassertion of CRSo Although this signal is used internally by the
SONIC-16 it is also provided as an output to the user
Receive Clock Input (RXCi)
from an external ENDEC (EXT e 1) The separated
received clock from the Manchester data stream This signal is generated from an
external ENDEC
Extended User Output (EXUSR1)
When EXBUS has been set (see section 432) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC-16
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 437)
TXD
TP
O
This pin will be TRI-STATE until the DCR has been written to (See section 432
EXBUS for more information)
EXUSR3
TRI
O Z
Transmit Data (TXD)
The serial NRZ data from the MAC unit which is to be decoded
by an external ENDEC Data is valid on the rising edge of TXC Although this signal is
used internally by the SONIC-16 it is also provided as an output to the user
Extended User Output (EXUSR3)
When EXBUS has been set (see section 432) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC-16
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 437)
TXE
TP
O
Transmit Enable
This pin is driven high when the SONIC-16 begins transmission and
remains active until the last byte is transmitted Although this signal is used internally by
the SONIC-16 it is also provided as an output to the user
TXCo
TRI
O Z
This pin will be TRI-STATE until the DCR has been written to (See section 432
EXBUS for more information)
TXCi
I
Transmit Clock Output (TXCo)
from the internal ENDEC (EXT e 0) This 10 MHz
STERM
I
clock transmit clock output is derived from the 20 MHz oscillator When EXT e 0 the
TXCOUT signal is internally connected between the ENDEC and MAC units Although
this signal is used internally by the SONIC-16 it is also provided as an output to the user
Transmit Clock Input (TXCi)
(EXT e 1) This input clock from an external ENDEC is
used for shifting data out of the MAC unit serializer This clock is nominally 10 MHz
Synchronous Termination (STERM)
When the SONIC-16 is a bus master it samples
this pin before terminating its memory cycle This pin is sampled synchronously and may
only be used in asynchronous bus mode when BMODE e 1 See section 545 for more
details
46



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