DP83916 datasheet(41/96 Pages) NSC

41 / 96 page

40 SONIC-16 Registers (Continued)

4310 CAM Registers

The CAM registers described in this section are part of the

User Register set They are used to program the Content

Addressable Memory (CAM) entries that provide address

filtering of packets These registers except for the CAM

Enable register are unaffected by a hardware or software

reset

CAM Entry Pointer Register (CEP)

The CEP is a 4-bit

entries SONIC-16 uses the least significant 4-bits of this

the value of Fh points to the last entry

CAM Address Port 2

0 Registers (CAP2

CAP1

CAP0)

Each CAP is a 16-bit read-only register used to ac-

cess the CAM cells Each CAM cell is 16-bits wide and con-

tains one third of the 48-bit CAM entry which is used by the

SONIC-16 for address filtering The CAP2 register is used to

access the upper bits (k4732l) CAP1 the middle bits

(k3116l) and CAP0 the lower bits (k150l) of the CAM

entry Given the physical address 102030405060 which

is made up of 6 octets or bytes where 10h is the least

significant byte and 60h is the most significant byte (10h

would be the first byte received from the network and 60h

would be the last) CAP0 would be loaded with 2010h CAP1

with 4030h and CAP2 with 6050h

To read a CAM entry the user first places the SONIC-16 in

software reset (set the RST bit in the Command register)

programs the CEP register to select one of sixteen CAM

entries then reads CAP2 CAP1 and CAP0 to obtain the

complete 48-bit entry The user can not write to the CAM

entries directly Instead the user programs the CAM de-

scriptor area in system memory (see section 411) then

issues the Load CAM command (setting LCAM bit in the

Command register) This causes the SONIC-16 to read the

descriptors from memory and loads the corresponding CAM

entry through CAP2-0

MSB

LSB

Destination Address

CAP2

CAP1

CAP0

CAM Enable Register (CE)

The CE is a 16-bit readwrite

Each register bit position corresponds to a CAM entry

When a register bit is set to a ‘‘1’’ the corresponding CAM

entry is enabled When ‘‘0’’ the entry is disabled This regis-

ter is unaffected by a software reset and cleared to zero

(disabling all entries) during a hardware reset Under normal

operations the user does not access this register Instead

the user sets up this register through the last entry in the

CAM descriptor area The SONIC-16 loads the CE register

during execution of the LCAM Command

CAM Descriptor Pointer Register (CDP)

The CDP is a

15-bit readwrite register The LSB is unused and always

reads back as 0 The CDP is programmed with the lower

address (Ak151l) of the first field of the CAM descriptor

block in the CAM descriptor area (CDA) of system memory

SONIC-16 uses the contents of the CDP register when ac-

cessing the CAM descriptors This register must be pro-

grammed by the user before issuing the LCAM command

During execution of the LCAM Command SONIC-16 concat-

enates the contents of this register with the contents of the

URRA register to form the complete 23-bit address During

the Load CAM operation this register is incremented to ad-

dress the fields in the CDA After the Load Command com-

pletes this register points to the next location after the CAM

Descriptor Area

CAM Descriptor Count Register (CDC)

The CDC is a

5-bit readwrite register It is programmed with the number

of CAM descriptor blocks in the CAM descriptor area This

LCAM command SONIC-16 uses the value in this register

to determine how many entries to place in the CAM during

execution of the LCAM command During LCAM execution

SONIC-16 decrements this register each time it reads a de-

scriptor block When the CDC decrements to zero SONIC-

16 terminates the LCAM execution Since the CDC register

is programmed with the number of CAM descriptor blocks in

the CAM Descriptor Area the value programmed into the

CDC register ranges 1 to 16 (1h to 10h)

4311 Tally Counters

The SONIC-16 provides three 16-bit counters used for mon-

itoring network statistics on the number of CRC errors

Frame Alignment errors and missed packets These regis-

ters rollover after the count of FFFFh is reached and pro-

duce an interrupt if enabled in the Interrupt Mask Register

(IMR) These counters are unaffected by the RXEN bit in the

CR but are halted when the RST bit in the CR is set The

data written to these registers is inverted before being

latched This means that if a value of FFFFh is written to

these registers by the system they will contain and read

back the value 0000h Data is not inverted during a read

operation The Tally registers therefore are cleared by writ-

ing all ‘‘1’s’’ to them A software or hardware reset does not

affect the tally counters

CRC Tally Counter Register (CRCT)

The CRCT is a 16-bit

readwrite register This register is used to keep track of the

number of packets received with CRC errors After a packet

is accepted by the address recognition logic this register is

incremented if a CRC error is detected If the packet also

contains a Frame Alignment error this counter is not incre-

mented

FAE Tally Counter Register (FAET)

The FAET is a 16-bit

readwrite register This register is used to keep track of the

number of packets received with frame alignment errors

After a packet is accepted by the address recognition logic

this register is incremented if a FAE error is detected

Missed Packet Tally Counter Register (MPT)

The MPT is

a 16-bit readwrite register After a packet is received this

counter is incremented if there is (1) lack of memory re-

sources to buffer the packet (2) a FIFO overrun or (3) a

valid packet has been received but the receiver is disabled

(RXDIS is set in the command register)

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