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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83916 датащи(PDF) 57 Page - National Semiconductor (TI) |
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DP83916 датащи(HTML) 57 Page - National Semiconductor (TI) |
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57 / 96 page  50 Bus Interface (Continued) 5452 Memory Cycle for BMODE e 1 Synchronous Mode On the rising edge of T1 the SONIC-16 asserts ECS to indicate that the memory cycle is starting The address (A31 – A1) bus status (S2 – S0) and the direction strobe (MRW) are driven and do not change for the remainder of the memory cycle On the falling edge of T1 the SONIC-16 deasserts ECS and asserts AS In synchronous mode DSACK01 are sampled on the rising edge of T2 T2 states will be repeated until DSACK01 are sampled properly in a low state DSACK01 must meet the setup and hold times with respect to the rising edge of bus clock for proper operation During read cycles ( Figure 5-8 ) data (D15 – D0) is latched at the falling edge of T2 and DS is asserted at the falling edge of T1 For write cycles ( Figure 5-9 ) data is driven on the falling edge of T1 If there are wait states inserted DS is asserted on the falling edge of T2 The SONIC-16 termi- nates the memory cycle by deasserting AS and DS at the falling edge of T2 TLF11722 – 31 FIGURE 5-8 Memory Read BMODEe1 Synchronous (1 Wait-State) TLF11722 – 33 FIGURE 5-9 Memory Write BMODEe1 Synchronous (1 Wait-State) 57 |
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