DP83916 datasheet(53/96 Pages) NSC

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50 Bus Interface (Continued)

541 Acquiring The Bus

The SONIC-16 requests the bus when 1) its FIFO threshold

has been reached or 2) when the descriptor areas in memo-

ry (ie RRA RDA CDA and TDA) are accessed Note that

when the SONIC-16 moves from one area in memory to

another (eg RBA to RDA) it always deasserts its bus re-

quest and then requests the bus again when accessing the

next area in memory

The SONIC-16 provides two methods to acquire the bus for

compatibility with NationalIntel or Motorola type microproc-

essors These two methods are selected by setting the

proper level on the BMODE pin

Figures 5-5 and 5-6 show the NationalIntel (BMODE e 0)

and Motorola (BMODE e 1) bus request timing Descrip-

tions of each mode follows For both modes when the

SONIC-16 relinquishes the bus there is an extra holding

state (Th) for one bus cycle after the last DMA cycle (T2)

This assures that the SONIC-16 does not contend with an-

other bus master after it has released the bus

BMODE e 0

The NationalIntel processors require a 2-way handshake

using a HOLD REQUESTHOLD ACKNOWLEDGE protocol

(

Figure 5-5 ) When the SONIC-16 needs to access the bus

it issues a HOLD REQUEST (HOLD) to the microprocessor

The microprocessor responds with a HOLD ACKNOWL-

EDGE (HLDA) to the SONIC-16 The SONIC-16 then begins

its memory transfers on the bus As long as the CPU main-

tains HLDA active the SONIC-16 continues until it has fin-

ished its memory block transfer The CPU however can

preempt the SONIC-16 from finishing the block transfer by

deasserting HLDA before the SONIC-16 deasserts HOLD

This allows a higher priority device to preempt the SONIC-

16 from continuing to use the bus The SONIC-16 will re-

quest the bus again later to complete any operation that it

was doing at the time of preemption

As shown in

Figure 5-5 the SONIC-16 will assert HOLD to

either the falling or rising edge of the bus clock (BSCK) The

default is for HOLD to be asserted on the falling edge Set-

ting the PH bit in the DCR2 (see Section 437) causes

HOLD to be asserted

bus clock later on the rising edge

(shown by the dotted line) Before HOLD is asserted the

SONIC-16 checks the HLDA line If HLDA is asserted

HOLD will not be asserted until after HLDA has been deas-

serted first

BMODE e 1

The Motorola protocol requires a 3-way handshake using a

BUS REQUEST

BUS GRANT

and BUS GRANT AC-

KNOWLEDGE handshake (

Figure 5-6 ) When using this

protocol the SONIC-16 requests the bus by lowering BUS

REQUEST (BR)

The CPU responds by issuing BUS

GRANT (BG) Upon receiving BG the SONIC-16 assures

that all devices have relinquished control of the bus before

using the bus The following signals must be deasserted

before the SONIC-16 acquires the bus

BGACK

DSACK01

STERM (Asynchronous Mode Only)

Deasserting BGACK indicates that the previous master has

released the bus Deasserting AS indicates that the previ-

ous master has completed its cycle and deasserting

DSACK01 and STERM indicates that the previous slave

has terminated its connection to the previous master The

SONIC-16 maintains its mastership of the bus until it deas-

serts BGACK It can not be preempted from the bus

TLF11722 – 27

FIGURE 5-5 Bus Request Timing BMODEe0

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