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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83916 датащи(PDF) 37 Page - National Semiconductor (TI) |
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DP83916 датащи(HTML) 37 Page - National Semiconductor (TI) |
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37 / 96 page  40 SONIC-16 Registers (Continued) 436 Interrupt Status Register (RAk50l e 5h) This register (Figure 4-9) indicates the source of an interrupt when the INT pin goes active Enabling the corresponding bits in the IMR allows bits in this register to produce an interrupt When an interrupt is active one or more bits in this register are set to a ‘‘1’’ A bit is cleared by writing ‘‘1’’ to it Writing a ‘‘0’’ to any bit has no effect This register is cleared by a hardware reset and unaffected by a software reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BR HBL LCD PINT PKTRX PTDN TXER TC RDE RBE RBAE CRC FAE MP RFO rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rwereadwrite FIGURE 4-9 Interrupt Status Register Field Meaning BR BUS RETRY OCCURRED HBL CD HEARTBEAT LOST LCD LOAD CAM DONE PINT PROGRAMMABLE INTERRUPT PKTRX PACKET RECEIVED TXDN TRANSMISSION DONE TXER TRANSMIT ERROR TC TIMER COMPLETE RDE RECEIVE DISCRIPTORS EXHAUSTED RBE RECEIVE BUFFERS EXHAUSTED RBAE RECEIVE BUFFER AREA EXCEEDED CRC CRC TALLY COUNTER ROLLOVER FAE FRAME ALIGNMENT ERROR MP MISSED PACKET COUNTER ROLLOVER RFO RECEIVE FIFO OVERRUN Bit Description 15 Must be 0 14 BR BUS RETRY OCCURRED Indicates that a Bus Retry (BRT) operation has occurred In Latched Bus Retry mode (LBR in the DCR) BR will only be set when the SONIC-16 is a bus master Before the SONIC-16 will continue any DMA operations BR must be cleared In Unlatched mode the BR bit should be cleared also but the SONIC-16 will not wait for BR to be cleared before requesting the bus again and continuing its DMA operations (See sections 432 and 546 for more information on Bus Retry) 13 HBL CD HEARTBEAT LOST If the transceiver fails to provide a collision pulse (heart beat) during the first 64 ms of the Interframe Gap after transmission this bit is set 12 LCD LOAD CAM DONE Indicates that the Load CAM command has finished writing to all programmed locations in the CAM (See section 411) 11 PINT PROGRAMMED INTERRUPT Indicates that upon reading the TXpktconfig field the SONIC-16 has detected the PINTR bit to be set (See section 434) 10 PKTRX PACKET RECEIVED Indicates that a packet has been received and been buffered to memory This bit is set after the RXpktseq no field is written to memory 9 TXDN TRANSMISSION DONE Indicates that either (1) there are no remaining packets to be transmitted in the Transmit Descriptor Area (ie the EOL bit has been detected as a ‘‘1’’) (2) the Halt Transmit command has been given (HTX bit in CR is set to a ‘‘1’’) or (3) a transmit abort condition has occurred This condition occurs when any of following bits in the TCR are set BCM EXC FU or EXD This bit is set after the TXpktstatus field has been written to 37 |
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