DP83916 datasheet(6/96 Pages) NSC

6 / 96 page

10 Functional Description (Continued)

During transmission of a packet from the SONIC-16 the

external transceiver will always loop the packet back to the

SONIC-16 The SONIC-16 will use this to monitor the packet

as it is being transmitted The CRC and source address of

the looped back packet are checked with the CRC and

source address that were transmitted If they do not match

an error bit is set in the status of the transmitted packet (see

Packet Monitored Bad PBM in the Transmit Control Regis-

ter section 434) Data is not written to the receive FIFO

during this monitoring process unless Transceiver Loopback

mode has been selected (see section 17)

Receive Logic

The receive logic contains the command

control and status registers that govern the operations of

the receive section It generates the control signals for writ-

ing data to the receive FIFO processes error signals ob-

tained from the CRC checker and the deserializer activates

the ‘‘packet reject’’ signal to the RSM for rejecting packets

and posts the applicable status in the Receive Control regis-

ter

Deserializer

This section deserializes the serial input data

stream and furnishes a byte clock for the address compara-

tor and receive logic It also synchronizes the CRC checker

to begin operation (after SFD is detected) and checks for

proper frame alignment with respect to CRS going inactive

at the end of reception

Address Comparator

The address comparator latches the

Destination Address (during reception or loopback) or

Source Address (during transmission) and determines

whether the address matches one of the entries in the CAM

(Content Addressable Memory)

CRC Checker

The CRC checker calculates the 4-byte

Frame Check Sequence (FCS) field from the incoming data

stream and compares it with the last 4-bytes of the received

packet The CRC checker is active for both normal recep-

tion and self-reception during transmission

Content Addressable Memory (CAM)

The CAM contains

16 user programmable entries and 1 pre-programmed

Broadcast address entry for complete filtering of received

packets The CAM can be loaded with any combination of

Physical and Multicast Addresses (section 22) See section

41 for the procedure on loading the CAM registers

122 MAC Transmit Section

The transmit section

(Figure 1-4 ) is responsible for reading

data from the transmit FIFO and transmitting a serial data

stream onto the network in conformance with the IEEE

8023 CSMACD standard The Transmit Section consists

of the following blocks

Transmit State Machine (TSM)

The TSM controls the

functions of the serializer preamble generator and JAM

generator It determines the proper sequence of events that

the transmitter follows under various network conditions If

no collision occurs the transmitter prefixes a 62-bit pream-

ble and 2-bit Start of Frame Delimiter (SFD) at the beginning

of each packet then sends the serialized data At the end of

the packet an optional 4-byte CRC pattern is appended If a

collision occurs the transmitter switches from transmitting

data to sending a 4-byte Jam pattern to notify all nodes that

a collision has occurred Should the collision occur during

the preamble the transmitter waits for it to complete before

jamming After the transmission has completed the trans-

mitter writes status in the Transmit Control register (section

434)

Protocol State Machine

The protocol state machine as-

sures that the SONIC-16 obeys the CSMACD protocol Be-

fore transmitting this state machine monitors the carrier

sense and collision signals for network activity If another

node(s) is currently transmitting the SONIC-16 defers until

the network is quiet then transmits after its Interframe Gap

Timer (96 ms) has expired The Interframe Gap time is divid-

ed into two portions During the first 64 ms network activity

restarts the Interframe Gap timer Beyond this time howev-

er network activity is ignored and the state machine waits

the remaining 32 ms before transmitting If the SONIC-16

experiences a collision during a transmission the SONIC-16

switches from transmitting data to a 4-byte JAM pattern (4

bytes of all 1’s) before ceasing to transmit The SONIC-16

then waits a random number of slot times (512 ms) deter-

mined by the

Truncated Binary Exponential Backoff Algo-

rithm before reattempting another transmission In this algo-

rithm the number of slot times to delay before the nth re-

transmission is chosen to be a random integer r in the range

0 s r s 2k

where k e min(n10)

If a collision occurs on the 16th transmit attempt the SON-

IC-16 aborts transmitting the packet and reports an ‘‘Exces-

sive Collisions’’ error in the Transmit Control register

TLF11722 – 5

FIGURE 1-4 MAC Transmitter

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