PI7C8150BMA-33 datasheet(32/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 32 of 107

April 2015 – Revision 2.1



Decodes the device number and drives the bit pattern specified in Table 3-6 on

S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.



Sets S_AD[15:11] to 0.



Leaves unchanged the function number and register number fields.

PI7C8150B asserts a unique address line based on the device number. These address lines

may be used as secondary bus IDSEL signals. The mapping of the address lines depends on

the device number in the Type 1 address bits P_AD[15:11]. presents the mapping that

PI7C8150B uses.

Table 3-6. Device Number to IDSEL S_AD Pin Mapping

Device Number

P_AD[15:11]

Secondary IDSEL S_AD[31:16]

S_AD

00000

0000 0000 0000 0001

00001

0000 0000 0000 0010

00010

0000 0000 0000 0100

00011

0000 0000 0000 1000

00100

0000 0000 0001 0000

00101

0000 0000 0010 0000

00110

0000 0000 0100 0000

00111

0000 0000 1000 0000

01000

0000 0001 0000 0000

01001

0000 0010 0000 0000

01010

0000 0100 0000 0000

01011

0000 1000 0000 0000

01100

0001 0000 0000 0000

01101

0010 0000 0000 0000

01110

0100 0000 0000 0000

01111

1000 0000 0000 0000

10h – 1Eh

10000 – 11110

0000 0000 0000 0000

1Fh

11111

Generate special cycle (P_AD[7:2] > 00h)

0000 0000 0000 0000 (P_AD[7:2] = 00h)

PI7C8150B can assert up to 9 unique address lines to be used as IDSEL signals for

up to 9 devices on the secondary bus, for device numbers ranging from 0 through 8.

Because of electrical loading constraints of the PCI bus, more than 9 IDSEL signals should

not be necessary. However, if device numbers greater than 9 are desired, some external

method of generating IDSEL lines must be used, and no upper address bits are then

asserted. The configuration transaction is still translated and passed from the primary bus to

the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends

in a master abort.

PI7C8150B forwards Type 1 to Type 0 configuration read or write transactions as delayed

transactions. Type 1 to Type 0 configuration read or write transactions are limited to a

single 32-bit data transfer.

3.7.3

TYPE 1 TO TYPE 1 FORWARDING

Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism

when two or more levels of PCI-to-PCI bridges are used.

When PI7C8150B detects a Type 1 configuration transaction intended for a PCI bus

downstream from the secondary bus, PI7C8150B forwards the transaction unchanged to the

secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command

or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1

15-0048

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