PI7C8150BMA-33 datasheet(75/107 Pages) PERICOM

75 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 75 of 107

April 2015 – Revision 2.1

14.1.2

DEVICE ID REGISTER – OFFSET 00h

Bit

Function

Type

Description

31:16

Device ID

R/O

Identifies this device as the PI7C8150B. Hardwired as 8150h.

14.1.3

COMMAND REGISTER – OFFSET 04h

Bit

Function

Type

Description

I/O Space Enable

R/W

Controls response to I/O access on the primary interface

0: ignore I/O transactions on the primary interface

1: enable response to I/O transactions on the primary interface

Reset to 0

Memory Space

Enable

R/W

Controls response to memory accesses on the primary interface

0: ignore memory transactions on the primary interface

1: enable response to memory transactions on the primary interface

Reset to 0

Bus Master

Enable

R/W

Controls ability to operate as a bus master on the primary interface

0: do not initiate memory or I/O transactions on the primary

interface and disable response to memory and I/O transactions on

the secondary interface

1: enables 7C8150 to operate as a master on the primary interfaces

for memory and I/O transactions forwarded from the secondary

interface

Reset to 0

Special Cycle

Enable

R/O

No special cycles defined.

Bit is defined as read only and returns 0 when read

Memory Write

And Invalidate

Enable

R/O

Memory write and invalidate not supported.

Bit is implemented as read only and returns 0 when read (unless

forwarding a transaction for another master)

VGA Palette

Snoop Enable

R/W

Controls response to VGA compatible palette accesses

0: ignore VGA palette accesses on the primary

1: enable positive decoding response to VGA palette writes on the

primary interface with I/O address bits AD[9:0] equal to 3C6h,

3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded

and may be any value)

Reset to 0

Parity Error

Response

R/W

Controls response to parity errors

0: 7C8150 may ignore any parity errors that it detects and continue

normal operation

1: 7C8150 must take its normal action when a parity error is

detected

Reset to 0

Wait Cycle

Control

R/O

Controls the ability to perform address / data stepping

0: disable address/data stepping (affects primary and secondary)

1: enable address/data stepping (affects primary and secondary)

Reset to 0

15-0048

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