PI7C8150BMA-33 datasheet(41/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 41 of 107

April 2015 – Revision 2.1

ADDRESS DECODING

PI7C8150B uses three address ranges that control I/O and memory transaction forwarding.

These address ranges are defined by base and limit address registers in the configuration

space. This chapter describes these address ranges, as well as ISA-mode and VGA-

addressing support.

4.1

ADDRESS RANGES

PI7C8150B uses the following address ranges that determine which I/O and memory

transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from

the secondary bus to the primary bus:



Two 32-bit I/O address ranges



Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges



Two 32-bit prefetchable memory address ranges

Transactions falling within these ranges are forwarded downstream from the primary PCI

bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded

upstream from the secondary PCI bus to the primary PCI bus.

No address translation is required in PI7C8150B. The addresses that are not marked for

downstream are always forwarded upstream.

4.2

I/O ADDRESS DECODING

PI7C8150B uses the following mechanisms that are defined in the configuration space to

specify the I/O address space for downstream and upstream forwarding:



I/O base and limit address registers



The ISA enable bit



The VGA mode bit



The VGA snoop bit

This section provides information on the I/O address registers and ISA mode. Section 4.4

provides information on the VGA modes.

To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the

command register in configuration space. All I/O transactions initiated on the primary bus

will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O

transactions, the master enable bit must be set in the command register. If the master-

enable bit is not set, PI7C8150B ignores all I/O and memory transactions initiated on the

secondary bus.

The master-enable bit also allows upstream forwarding of memory transactions if it is set.

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