PI7C8150BMA-33 datasheet(48/107 Pages) PERICOM

48 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 48 of 107

April 2015 – Revision 2.1



The ordering relationship of a transaction with respect to other transactions is

determined when the transaction completes, that is, when a transaction ends with a

termination other than target retry.



Requests terminated with target retry can be accepted and completed in any order with

respect to other transactions that have been terminated with target retry. If the order of

completion of delayed requests is important, the initiator should not start a second

delayed transaction until the first one has been completed. If more than one delayed

transaction is initiated, the initiator should repeat all delayed transaction requests,

using some fairness algorithm. Repeating a delayed transaction cannot be contingent

on completion of another delayed transaction. Otherwise, a deadlock can occur.



Write transactions flowing in one direction have no ordering requirements with respect

to write transactions flowing in the other direction. PI7C8150B can accept posted write

transactions on both interfaces at the same time, as well as initiate posted write

transactions on both interfaces at the same time.



The acceptance of a posted memory write transaction as a target can never be

contingent on the completion of a non-locked, non-posted transaction as a master. This

is true for PI7C8150B and must also be true for other bus agents. Otherwise, a

deadlock can occur.



PI7C8150B accepts posted write transactions, regardless of the state of completion of

any delayed transactions being forwarded across PI7C8150B.

5.3

ORDERING RULES

Table 5-1 shows the ordering relationships of all the transactions and refers by number to

the ordering rules that follow.

Table 5-1. Summary of Transaction Ordering

Pass

Posted

Write

Delayed

Read

Request

Delayed

Write

Request

Delayed Read

Completion

Delayed Write

Completion

Posted Write

Yes

Delayed Read Request

Yes

Delayed Write Request

Yes

Delayed Read

Completion

Yes

Delayed Write

Completion

Yes

Note: The superscript accompanying some of the table entries refers to any applicable

ordering rule listed in this section. Many entries are not governed by these ordering rules;

therefore, the implementation can choose whether or not the transactions pass each other.

The entries without superscripts reflect the PI7C8150B’s implementation choices.

The following ordering rules describe the transaction relationships. Each ordering rule is

followed by an explanation, and the ordering rules are referred to by number in Table 5-1.

These ordering rules apply to posted write transactions, delayed write and read requests,

and delayed write and read completion transactions crossing PI7C8150B in the same

direction. Note that delayed completion transactions cross PI7C8150B in the direction

opposite that of the corresponding delayed requests.

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