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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PI7C8150BMA-33 датащи(PDF) 85 Page - Pericom Semiconductor Corporation |
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PI7C8150BMA-33 датащи(HTML) 85 Page - Pericom Semiconductor Corporation |
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85 / 107 page  PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 85 of 107 April 2015 – Revision 2.1 14.1.32 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Type Description 16 Upstream (S to P) Memory Base and Limit Enable R/W 0: Upstream memory is the entire range except the down stream memory channel 1: Upstream memory is confined to upstream Memory Base and Limit (See offset 50 th and 54th for upstream memory range) Reset to 0 31:17 Reserved R/O Reserved. Returns 0 when read. 14.1.33 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch Bit Function Type Description 31:28 Secondary bus arbiter preemption contorl R/W Controls the number of clock cycles after frame is asserted before preemption is enabled. 1xxx: Preemption off 0000: Preemption enabled after 0 clock cycles 0001: Preemption enabled after 1 clock cycle 0010: Preemption enabled after 2 clock cycles 0011: Preemption enabled after 4 clock cycles 0100: Preemption enabled after 8 clock cycles 0101: Preemption enabled after 16 clock cycles 0110: Preemption enabled after 32 clock cycles 0111: Preemption enabled after 64 clock cycles Reset to 0000 27:0 Hot Swap Switch Time Slot Register (15K PCI clocks R/W Default is 0003A98 14.1.34 UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h Bit Function Type Description 3:0 64 bit addressing R/O 0: 32 bit addressing 1: 64 bit addressing Reset to 1 15:4 Upstream Memory Base Address R/W Controls upstream memory base address. Reset to 00000000h 14.1.35 UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h Bit Function Type Description 19:16 64 bit addressing R/O 0: 32 bit addressing 1: 64 bit addressing Reset to 1 15-0048 |
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