PI7C8150BMA-33 datasheet(49/107 Pages) PERICOM

49 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 49 of 107

April 2015 – Revision 2.1

1. Posted write transactions must complete on the target bus in the order in which they

were received on the initiator bus. The subsequent posted write transaction can be setting a

flag that covers the data in the first posted write transaction; if the second transaction were

to complete before the first transaction, a device checking the flag could subsequently

consume stale data.

2. A delayed read request traveling in the same direction as a previously queued posted

write transaction must push the posted write data ahead of it. The posted write transaction

must complete on the target bus before the delayed read request can be attempted on the

target bus. The read transaction can be to the same location as the write data, so if the read

transaction were to pass the write transaction, it would return stale data.

3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data

traveling in the same direction. In this case, the read data is traveling in the same direction

as the write data, and the initiator of the read transaction is on the same side of PI7C8150B

as the target of the write transaction. The posted write transaction must complete to the

target before the read data is returned to the initiator. The read transaction can be a reading

to a status register of the initiator of the posted write data and therefore should not

complete until the write transaction is complete.

4. Delayed write requests cannot pass previously queued posted write data. For posted

memory write transactions, the delayed write transaction can set a flag that covers the data

in the posted write transaction. If the delayed write request were to complete before the

earlier posted write transaction, a device checking the flag could subsequently consume

stale data.

5. Posted write transactions must be given opportunities to pass delayed read and write

requests and completions. Otherwise, deadlocks may occur when some bridges which

support delayed transactions and other bridges which do not support delayed transactions

are being used in the same system. A fairness algorithm is used to arbitrate between the

posted write queue and the delayed transaction queue.

5.4

DATA SYNCHRONIZATION

Data synchronization refers to the relationship between interrupt signaling and data

delivery. The PCI Local Bus Specification, Revision 2.3, provides the following alternative

methods for synchronizing data and interrupts:



The device signaling the interrupt performs a read of the data just written (software).



The device driver performs a read operation to any register in the interrupting device

before accessing data written by the device (software).



System hardware guarantees that write buffers are flushed before interrupts are

forwarded.

PI7C8150B does not have a hardware mechanism to guarantee data synchronization for

posted write transactions. Therefore, all posted write transactions must be followed by a

read operation, either from the device to the location just written (or some other location

along the same path), or from the device driver to one of the device registers.

15-0048

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