PI7C8150BMA-33 datasheet(78/107 Pages) PERICOM

78 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 78 of 107

April 2015 – Revision 2.1

14.1.12

SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h

Bit

Function

Type

Description

23:16

Subordinate Bus

Number

R/W

Indicates the number of the PCI bus with the highest number that is

subordinate to the bridge. The value is set in software during

configuration.

Reset to 0

14.1.13

SECONDARY LATENCY TIMER REGISTER – OFFSET 18h

Bit

Function

Type

Description

31:24

Secondary

Latency Timer

R/W

Latency timer for secondary. Indicates the number of PCI clocks

from the assertion of S_FRAME_L to the expiration of the timer

when the Bridge is acting as a master on the secondary.

0: Bridge ends the transaction after the first data transfer when the

Bridge’s secondary bus grant has been deasserted, with the

exception of memory write and invalidate transactions.

Reset to 0

14.1.14

I/O BASE REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

3:0

32-bit Indicator

R/O

Read as 01h to indicate 32-bit I/O addressing

7:4

I/O Base Address

[15:12]

R/W

Defines the bottom address of the I/O address range for the bridge

to determine when to forward I/O transactions from one interface to

the other. The upper 4 bits correspond to address bits [15:12] and

are writable. The lower 12 bits corresponding to address bits [11:0]

are assumed to be 0. The upper 16 bits corresponding to address

bits [31:16] are defined in the I/O base address upper 16 bits address

Reset to 0

14.1.15

I/O LIMIT REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

11:8

32-bit Indicator

R/O

Read as 01h to indicate 32-bit I/O addressing

15:12

I/O Base Address

[15:12]

R/W

Defines the top address of the I/O address range for the bridge to

determine when to forward I/O transactions from one interface to

the other. The upper 4 bits correspond to address bits [15:12] and

are writable. The lower 12 bits corresponding to address bits [11:0]

are assumed to be FFFh. The upper 16 bits corresponding to

address bits [31:16] are defined in the I/O base address upper 16 bits

address register

Reset to 0

14.1.16

SECONDARY STATUS REGISTER – OFFSET 1Ch

Bit

Function

Type

Description

20:16

Reserved

R/O

Reset to 0

66MHz Capable

R/O

Set to 1 to enable 66MHz operation on the secondary interface

Reset to 1

Reserved

R/O

Reset to 0

Fast Back-to-

Back Capable

R/O

Set to 1 to enable decoding of fast back-to-back transactions on the

secondary interface to different targets

Reset to 1

15-0048

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