PI7C8150BMA-33 datasheet(69/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 69 of 107

April 2015 – Revision 2.1

Table 10-2. GPIO Serial Data Format

Bit

Description

S_CLKOUT

[1:0]

Slot 0 PRSNT#[1:0] or device 0

[3:2]

Slot 1 PRSNT#[1:0] or device 1

[5:4]

Slot 2 PRSNT#[1:0] or device 2

[7:6]

Slot 3 PRSNT#[1:0] or device 3

[8]

Device 4

[9]

Device 5

[10]

Device 6

[11]

Device 7

[12]

Device 8

[13]

PI7C8150B S_CLKIN

[14]

Reserved

[15]

Reserved

The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control

the S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that

indicates that a card is present in the slot and therefore the secondary clock for that slot is

not masked. If these clocks are connected to devices and not to slots, one or both of the bits

should be tied low to enable the clock.

The next 5 bits are the clock mask for devices; each bit enables or disables the clock for

one device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1

disables the clock.

Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8150B’s

S_CLKIN input.

If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8150B’s

S_CLKIN input can be rearranged from the assignment shown here. However, it is

important that the serial data stream format match the assignment of S_CLKOUT.

The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits

are tied high to disable their respective secondary clocks because those clocks are not

connected to anything. The next bit is tied LOW because that secondary clock output is

connected to the PI7C8150B S_CLKIN input. When the secondary reset signal, S_RST_L,

is detected asserted and the primary reset signal, P_RST_L, is detected deasserted,

PI7C8150B drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift

This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the

least significant bit is shifted in last.

After the shift operation is complete, PI7C8150B tri-states the GPIO signals and can

deassert S_RST_L if the secondary reset bit is clear. PI7C8150B then ignores MSK_IN.

Control of the GPIO signal now reverts to PI7C8150B GPIO control registers. The clock

disable mask can be modified subsequently through a configuration write command to the

secondary clock control register in device-specific configuration space.

10.3

LIVE INSERTION

The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction

forwarding.

To enable live insertion mode, the live insertion mode bit in the chip control register must

be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO

output enable control register. When live insertion mode is enabled, whenever GPIO[3] is

15-0048

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