PI7C8150BMA-33 datasheet(83/107 Pages) PERICOM

83 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 83 of 107

April 2015 – Revision 2.1

14.1.29

DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h

Bit

Function

Type

Description

Reserved

R/O

Reserved. Returns 0 when read.

Memory Write

Disconnect

Control

R/W

Controls when the bridge (as a target) disconnects memory write

transactions.

0: memory write disconnects at 4KB aligned address boundary

1: memory write disconnects at cache line aligned address boundary

Reset to 0

3:2

Reserved

R/O

Reserved. Returns 0 when read.

Secondary Bus

Prefetch Disable

R/W

Controls the bridge’s ability to prefetch during upstream memory

read transactions.

0: The bridge prefetches and does not forward byte enable bits during

upstream memory reads.

1: The bridge requests only 1 DWORD from the target and forwards

read byte enable bits during upstream memory reads.

Reset to 0

Live Insertion

Mode

R/W

Enables hardware control of transaction forwarding.

0: GPIO[3] has no effect on the I/O, memory, and master enable bits

1: If GPIO[3] is set to input mode, this bit enables GPIO[3] to mask

I/O enable, memory enable and master enable bits to 0. PI7C8150B

will stop accepting I/O and memory transactions as a result.

Reset to 0

7:6

Reserved

R/O

Reserved. Returns 0 when read.

Chip Reset

R/WR

Controls the chip and secondary bus reset.

0: PI7C8150B is ready for operation

1: Causes PI7C8150B to perform a chip reset

Reset to 0

10:9

Test Mode For

All Counters at P

and S1

R/O

Controls the testability of the bridge’s internal counters.

The bits are used for chip test only.

00: all bits are exercised

01: byte 1 is exercised

10: byte 2 is exercised

11: byte 3 is exercised

Reset to 0

15:11

Reserved

R/O

Reserved. Returns 0 when read.

15-0048

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