PI7C8150BMA-33 datasheet(64/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 64 of 107

April 2015 – Revision 2.1

8.2

SECONDARY PCI BUS ARBITRATION

PI7C8150B implements an internal secondary PCI bus arbiter. This arbiter supports eight

external masters on the secondary bus in addition to PI7C8150B. The internal arbiter can

be disabled, and an external arbiter can be used instead for secondary bus arbitration.

8.2.1

SECONDARY BUS ARBITRATION USING THE INTERNAL

ARBITER

To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN_L, must be tied

LOW. PI7C8150B has nine secondary bus request input pins, S_REQ_L[8:0], and has nine

secondary bus output grant pins, S_GNT_L[8:0], to support external secondary bus masters.

The secondary bus request and grant signals are connected internally to the arbiter and are

not brought out to external pins when S_CFN_L is HIGH.

Figure 8-1

Secondary Arbiter Example

The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each

set taking care of 9 requests / grants. Each set of masters can be assigned to a high priority

group and a low priority group. The low priority group as a whole represents one entry in

the high priority group; that is, if the high priority group consists of n masters, then in at

least every n+1 transactions the highest priority is assigned to the low priority group.

Priority rotates evenly among the low priority group. Therefore, members of the high

priority group can be serviced n transactions out of n+1, while one member of the low

priority group is serviced once every n+1 transactions. Figure 9–1 shows an example of an

internal arbiter where four masters, including PI7C8150B, are in the high priority group,

and five masters are in the low priority group. Using this example, if all requests are always

asserted, the highest priority rotates among the masters in the following fashion (high

priority members are given in italics, low priority members, in boldface type): B, m0, m1,

m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2, m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7

and so on.

Each bus master, including PI7C8150B, can be configured to be in either the low priority

group or the high priority group by setting the corresponding priority bit in the arbiter-

control register. The arbiter-control register is located at offset 40h. Each master has a

corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If

the bit is set to 0, the master is assigned to the low priority group. If all the masters are

assigned to one group, the algorithm defaults to a straight rotating priority among all the

masters. After reset, all external masters are assigned to the low priority group, and

PI7C8150B is assigned to the high priority group. PI7C8150B receives highest priority on

the target bus every other transaction and priority rotates evenly among the other masters.

15-0048

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