PI7C8150BMA-33 datasheet(71/107 Pages) PERICOM

71 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 71 of 107

April 2015 – Revision 2.1

RESET

This chapter describes the primary interface, secondary interface, and chip reset

mechanisms.

12.1

PRIMARY INTERFACE RESET

PI7C8150B has a reset input, P_RESET_L. When P_RESET_L is asserted, the following

events occur:



PI7C8150B immediately tri-states all primary and secondary PCI interface signals.



PI7C8150B performs a chip reset.



Registers that have default values are reset.

P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and

S_CLKOUT. PI7C8150B is not accessible during P_RESET_L. After P_RESET_L is de-

asserted, PI7C8150B remains inaccessible for 16 PCI clocks before the first configuration

transaction can be accepted.

12.2

SECONDARY INTERFACE RESET

PI7C8150B is responsible for driving the secondary bus reset signals, S_RESET_L.

PI7C8150B asserts S_RESET_L when any of the following conditions are met:

Signal P_RESET_L is asserted. Signal S_RESET_L remains asserted as long as

P_RESET_L is asserted and does not de-assert until P_RESET_L is de-asserted.

The secondary reset bit in the bridge control register is set. Signal S_RESET_L

remains asserted until a configuration write operation clears the secondary reset bit.

S_RESET_L pin is asserted. When S_RESET_L is asserted, PI7C8150B immediately 3-

states all the secondary PCI interface signals associated with the secondary port. The

S_RESET_L in asserting and de-asserting edges can be asynchronous to P_CLK.

When S_RESET_L is asserted, all secondary PCI interface control signals, including the

secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE[3:0]#, S_PAR

are driven low for the duration of S_RESET_L assertion. All posted write and delayed

transaction data buffers are reset. Therefore, any transactions residing inside the buffers at

the time of secondary reset are discarded.

When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150B remains

accessible during secondary interface reset and continues to respond to accesses to its

configuration space from the primary interface.

12.3

CHIP RESET

The chip reset bit in the diagnostic control register can be used to reset the PI7C8150B and

the secondary bus.

15-0048

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