PI7C8150BMA-33 datasheet(26/107 Pages) PERICOM

26 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 26 of 107

April 2015 – Revision 2.1

timer expires, PI7C8150B discards the delayed write completion from the delayed

transaction completion queue. PI7C8150B also conditionally asserts P_SERR_L

(see Section 6.4).

3.5.4

WRITE TRANSACTION ADDRESS BOUNDARIES

PI7C8150B imposes internal address boundaries when accepting write data. The aligned

address boundaries are used to prevent PI7C8150B from continuing a transaction over a

device address boundary and to provide an upper limit on maximum latency. PI7C78150

returns a target disconnect to the initiator when it reaches the aligned address boundaries

under conditions shown in Table 3-3.

Table 3-3. Write Transaction Disconnect Address Boundaries

Type of Transaction

Condition

Aligned Address Boundary

Delayed Write

All

Disconnects after one data transfer

Posted Memory Write

Memory write disconnect control

bit = 0

(1)

4KB aligned address boundary

Posted Memory Write

Memory write disconnect control

bit = 1

(1)

Disconnects at cache line boundary

Posted Memory Write and

Invalidate

Cache line size  1, 2, 4, 8, 16

4KB aligned address boundary

Posted Memory Write and

Invalidate

Cache line size = 1, 2, 4, 8, 16

Cache line boundary if posted memory

write data FIFO does not have enough

space for the cache line

Note 1.

Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the

configuration space.

3.5.5

BUFFERING MULTIPLE WRITE TRANSACTIONS

PI7C8150B continues to accept posted memory write transactions as long as space for at

least one DWORD of data in the posted write data buffer remains. If the posted write data

buffer fills before the initiator terminates the write transaction, PI7C8150B returns a target

disconnect to the initiator.

Delayed write transactions are posted as long as at least one open entry in the delayed

transaction queue exists. Therefore, several posted and delayed write transactions can exist

in data buffers at the same time. See Chapter 6 for information about how multiple posted

and delayed write transactions are ordered.

3.5.6

FAST BACK-TO-BACK TRANSACTIONS

PI7C8150B can recognize and post fast back-to-back write transactions.

When PI7C8150B cannot accept the second transaction because of buffer

space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit

must be set in the command register for upstream write transactions, and in the bridge

control register for downstream write transactions.

15-0048

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