PI7C8150BMA-33 datasheet(29/107 Pages) PERICOM

29 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 29 of 107

April 2015 – Revision 2.1

3.6.5

DELAYED READ COMPLETION WITH TARGET

When delayed read request reaches the head of the delayed transaction queue, PI7C8150B

arbitrates for the target bus and initiates the read transaction only if all previously queued

posted write transactions have been delivered. PI7C8150B uses the exact read address and

read command captured from the initiator during the initial delayed read request to initiate

the read transaction. If the read transaction is a non-prefetchable read, PI7C8150B drives

the captured byte enable bits during the next cycle. If the transaction is a prefetchable read

transaction, it drives all byte enable bits to zero for all data phases. If PI7C8150B receives

a target retry in response to the read transaction on the target bus, it continues to repeat the

read transaction until at least one data transfer is completed, or until an error condition is

encountered. If the transaction is terminated via normal master termination or target

disconnect after at least one data transfer has been completed, PI7C8150B does not initiate

any further attempts to read more data.

If PI7C8150B is unable to obtain read data from the target after 2

24 (default) or 232

(maximum) attempts, PI7C8150B will report system error. The number of attempts is

programmable. PI7C8150B also asserts P_SERR_L if the primary SERR_L enable bit is

set in the command register. See Section 6.4 for information on the assertion of P_SERR_L.

Once PI7C8150B receives DEVSEL_L and TRDY_L from the target, it transfers the data

read to the opposite direction read data queue, pointing toward the opposite inter-face,

before terminating the transaction. For example, read data in response to a downstream

read transaction initiated on the primary bus is placed in the upstream read data queue. The

PI7C8150B can accept one DWORD of read data each PCI clock cycle; that is, no master

wait states are inserted. The number of DWORD’s transferred during a delayed read

transaction depends on the conditions given in Table 3-4 (assuming no disconnect is

received from the target).

3.6.6

DELAYED READ COMPLETION ON INITIATOR BUS

When the transaction has been completed on the target bus, and the delayed read data is at

the head of the read data queue, and all ordering constraints with posted write transactions

have been satisfied, the PI7C8150B transfers the data to the initiator when the initiator

repeats the transaction. For memory read transactions, PI7C8150B aliases the memory read,

memory read line, and memory read multiple bus commands when matching the bus

command of the transaction to the bus command in the delayed transaction queue.

PI7C8150B returns a target disconnect along with the transfer of the last DWORD of read

data to the initiator. If PI7C8150B initiator terminates the transaction before all read data

has been transferred, the remaining read data left in data buffers is discarded.

When the master repeats the transaction and starts transferring prefetchable read data from

data buffers while the read transaction on the target bus is still in progress and before a read

boundary is reached on the target bus, the read transaction starts operating in flow-through

mode. Because data is flowing through the data buffers from the target to the initiator, long

read bursts can then be sustained. In this case, the read transaction is allowed to continue

until the initiator terminates the transaction, or until an aligned 4KB address boundary is

reached, or until the buffer fills, whichever comes first. When the buffer empties,

PI7C8150B reflects the stalled condition to the initiator by disconnecting the initiator with

data. The initiator may retry the transaction later if data are needed. If the initiator does not

need any more data, the initiator will not continue the disconnected transaction. In this case,

PI7C8150B will start the master timeout timer. The remaining read data will be discarded

after the master timeout timer expires. To provide better latency, if there are any other

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