PI7C8150BMA-33 datasheet(95/107 Pages) PERICOM

95 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 95 of 107

April 2015 – Revision 2.1

read data. Again, the PAR signal corresponds to read data from the previous data phase

cycle.

15.2.3

REPORTING PARITY ERRORS

For all address phases, if a parity error is detected, the error should be reported on the

P_SERR_L signal by asserting P_SERR_L for one cycle and then 3-stating two cycles

after the bad address. P_SERR_L can only be asserted if bit 6 and 8 in the Command

asserting the P_PERR_L signal two cycles after the data phase and should remain asserted

for one cycle when bit 6 in the Command register is set to a 1.

The target reports any type of data parity errors during write cycles, while the master

reports data parity errors during read cycles.

Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim

the bus (P_DEVSEL_L remains inactive) and the cycle will then terminate with a Master

Abort. When the bridge is acting as master, a data parity error during a read cycle results in

the bridge master initiating a Master Abort.

15.2.4

SECONDARY IDSEL MAPPING

When PI7C8150B detects a Type 1 configuration transaction for a device connected to

the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream

interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device

number. This is translated to S_AD[31:16] by PI7C8150B.

IEEE 1149.1 COMPATIBLE JTAG CONTROLLER

An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins

are provided to support boundary scan in PI7C8150B for board-level continuity test and

diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital

input, output, input/output pins are tested except TAP pins.

The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and

a group of test data registers including Bypass and Boundary Scan registers. The TAP

controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test

Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the

machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not

active when the PCI resource is operating PCI bus cycles.

PI7C8150B implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and

EXTEST.

16.1

BOUNDARY SCAN ARCHITECTURE

Boundary-scan test logic consists of a boundary-scan register and support logic. These are

accessed through a Test Access Port (TAP). The TAP provides a simple serial interface

that allows all processor signal pins to be driven and/or sampled, thereby providing direct

control and monitoring of processor pins at the system level.

15-0048

PI7C8150BMA-33 датащи(PDF) 95 Page - Pericom Semiconductor Corporation

PI7C8150BMA-33 датащи(HTML) 95 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL