PI7C8150BMA-33 datasheet(25/107 Pages) PERICOM

25 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 25 of 107

April 2015 – Revision 2.1

If offset 74h bits [8:7] = 00, the PI7C8150b converts Memory Write and Invalidate

transactions to Memory Write transactions at the destination.

If the value in the cache line size register does meet the memory write and invalidate

conditions, the PI7C8150B returns a target disconnect to the initiator on a cache line

boundary.

3.5.3

DELAYED WRITE TRANSACTIONS

Delayed write forwarding is used for I/O write transactions and Type 1 configuration write

transactions.

A delayed write transaction guarantees that the actual target response is returned back to

the initiator without holding the initiating bus in wait states. A delayed write transaction is

limited to a single DWORD data transfer.

When a write transaction is first detected on the initiator bus, and PI7C8150B forwards it

as a delayed transaction, PI7C8150B claims the access by asserting DEVSEL_L and

returns a target retry to the initiator. During the address phase, PI7C8150B samples the bus

command, address, and address parity one cycle later. After IRDY_L is asserted,

PI7C8150B also samples the first data DWORD, byte enable bits, and data parity. This

information is placed into the delayed transaction queue. The transaction is queued only if

no other existing delayed transactions have the same address and command, and if the

delayed transaction queue is not full. When the delayed write transaction moves to the head

of the delayed transaction queue and all ordering constraints with posted data are satisfied.

The PI7C8150B initiates the transaction on the target bus. PI7C8150B transfers the write

data to the target. If PI7C8150B receives a target retry in response to the write transaction

on the target bus, it continues to repeat the write transaction until the data transfer is

completed, or until an error condition is encountered.

If PI7C8150B is unable to deliver write data after 2

24 (default) or 232 (maximum) attempts,

PI7C8150B will report a system error. PI7C8150B also asserts P_SERR_L if the primary

SERR_L enable bit is set in the command register. See Section 6.4 for information on the

assertion of P_SERR_L. When the initiator repeats the same write transaction (same

command, address, byte enable bits, and data), and the completed delayed transaction is at

the head of the queue, the PI7C8150B claims the access by asserting DEVSEL_L and

returns TRDY_L to the initiator, to indicate that the write data was transferred. If the

initiator requests multiple DWORD, PI7C8150B also asserts STOP_L in conjunction with

TRDY_L to signal a target disconnect. Note that only those bytes of write data with valid

byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH),

the corresponding byte of write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the target,

PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a target

retry to the initiator until write data is delivered to the target, or until an error condition is

encountered. When the write transaction is repeated, PI7C8150B does not make a new

entry into the delayed transaction queue. Section 3.8.3.1 provides detailed information

about how PI7C8150B responds to target termination during delayed write transactions.

PI7C8150B implements a discard timer that starts counting when the delayed write

completion is at the head of the delayed transaction completion queue.

The initial value of this timer can be set to the retry counter register offset 78h.

If the initiator does not repeat the delayed write transaction before the discard

15-0048

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