PI7C8150BMA-33 datasheet(36/107 Pages) PERICOM

36 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 36 of 107

April 2015 – Revision 2.1

PI7C8150B asserts P_SERR_L if the master-abort-on-posted-write is not set. The master-

abort-on-posted-write bit is bit 4 of the P_SERR_L event disable register (offset 64h).

Note: When PI7C8150B performs a Type 1 to special cycle conversion, a master abort is

the expected termination for the special cycle on the target bus. In this case, the master

abort received bit is not set, and the Type 1 configuration transaction is disconnected after

the first data phase.

3.8.3

TARGET TERMINATION RECEIVED BY PI7C8150B

When PI7C8150B initiates a transaction on the target bus and the target responds with

DEVSEL_L, the target can end the transaction with one of the following types of

termination:



Normal termination (upon de-assertion of FRAME_L)



Target retry



Target disconnect



Target abort

PI7C8150B handles these terminations in different ways, depending on the type of

transaction being performed.

3.8.3.1

DELAYED WRITE TARGET TERMINATION RESPONSE

When PI7C8150B initiates a delayed write transaction, the type of target termination

received from the target can be passed back to the initiator. Table 3-7 shows the response

to each type of target termination that occurs during a delayed write transaction.

PI7C8150B repeats a delayed write transaction until one of the following conditions is met:



PI7C8150B completes at least one data transfer.



PI7C8150B receives a master abort.



PI7C8150B receives a target abort.

PI7C8150B makes 2

24 (default) or 232 (maximum) write attempts resulting in a response of

target retry.

Table 3-7. Delayed Write Target Termination Response

Target Termination

Response

Normal

Returning disconnect to initiator with first data transfer only if multiple data

phases requested.

Target Retry

Returning target retry to initiator. Continue write attempts to target

Target Disconnect

Returning disconnect to initiator with first data transfer only if multiple data

phases requested.

Target Abort

Returning target abort to initiator. Set received target abort bit in target interface

status register. Set signaled target abort bit in initiator interface status register.

15-0048

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