PI7C8150BMA-33 datasheet(23/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 23 of 107

April 2015 – Revision 2.1

3.2

SINGLE ADDRESS PHASE

A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and

the bus command is driven on P_CBE[3:0]. PI7C8150B supports the linear increment

address mode only, which is indicated when the lowest two address bits are equal to zero.

If either of the lowest two address bits is nonzero, PI7C8150B automatically disconnects

the transaction after the first data transfer.

3.3

DEVICE SELECT (DEVSEL_L) GENERATION

PI7C8150B always performs positive address decoding (medium decode) when accepting

transactions on either the primary or secondary buses. PI7C8150B never does subtractive

decode.

3.4

DATA PHASE

The address phase of a PCI transaction is followed by one or more data phases. A data

phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted. A

transfer of data occurs only when both IRDY_L and TRDY_L are asserted during the same

PCI clock cycle. The last data phase of a transaction is indicated when FRAME_L is de-

asserted and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L are

asserted. See Section 3.8 for further discussion of transaction termination.

Depending on the command type, PI7C8150B can support multiple data phase PCI

transactions. For detailed descriptions of how PI7C8150B imposes disconnect boundaries,

see Section 3.5.4 for write address boundaries and Section 3.6.3 read address boundaries.

3.5

WRITE TRANSACTIONS

Write transactions are treated as either posted write or delayed write transactions. Table

3-2 shows the method of forwarding used for each type of write operation.

Table 3-2. Write Transaction Forwarding

Type of Transaction

Type of Forwarding

Memory Write

Posted (except VGA memory)

Memory Write and Invalidate

Posted

Memory Write to VGA memory

Delayed

I/O Write

Delayed

Type 1 Configuration Write

Delayed

3.5.1

MEMORY WRITE TRANSACTIONS

Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”

transactions.

When PI7C8150B determines that a memory write transaction is to be forwarded across the

bridge, PI7C8150B asserts DEVSEL_L with medium timing and TRDY_L in the next

cycle, provided that enough buffer space is available in the posted memory write queue for

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